A low-voltage-differential-signaling (LVDS) fault detector includes first and second LVDS lines, and a window comparator provides a first output indicating whether a difference between voltages at the first and second LVDS lines is greater than a threshold voltage, and a second output indicating whether a difference between the voltages at the second and first LVDS lines is greater than the threshold voltage. A charge circuit charges a capacitive node when either the first or second output is at a logic low, and discharges the capacitive node when neither the first nor second output is at a logic low. A Schmitt trigger generates a fault flag if charge on the capacitive node falls to a threshold.

A low-voltage-differential-signaling (LVDS) fault detector includes first and second LVDS lines, and a window comparator provides a first output indicating whether a difference between voltages at the first and second LVDS lines is greater than a threshold voltage, and a second output indicating whether a difference between the voltages at the second and first LVDS lines is greater than the threshold voltage. A charge circuit charges a capacitive node when either the first or second output is at a logic low, and discharges the capacitive node when neither the first nor second output is at a logic low. A Schmitt trigger generates a fault flag if charge on the capacitive node falls to a threshold.

The present invention relates to a method for testing a device under test. A component of the device under test generates or receives a bus signal, wherein the bus signal comprises a first data signal or a second data signal, and wherein an amplitude of the first data signal is different from an amplitude of the second data signal. A measurement instrument measures an amplitude of the bus signal. Further, it is determined whether the bus signal comprises the first data signal or the second data signal, based on the measured amplitude of the bus signal.

Aspects of the present disclosure are directed to assessing integrity of communications circuitry. As may be implemented in accordance with one or more embodiments, a circuit node carries out a test protocol utilizing characteristics of a communication protocol to detect potential integrity issues. An initial test bit sequence is transmitted to circuit nodes connected to signal lines of a bus, by providing a test voltage across the signal lines that is less than an operating voltage potential of the bus. An ensuing state of the bus is sensed, and integrity of the bus or of circuitry connected to the bus is assessed based on the sensed state of the bus and on a state that the bus is expected to be in after transmission of the initial test bit sequence, which is used as an indication of whether all of the circuit nodes received the initial test bit sequence.

A differential signal measurement system is provided. The differential signal measurement system includes a measurement device, with at least one differential signal input, a differential connection interface configured to connect the at least one differential signal input of the measurement device to a device under test, and a differential signal source, with at least one differential signal output, configured to generate at least one differential output signal. The differential connection interface is further configured to pass the at least one differential output signal to the at least one differential signal input of the measurement device, and the measurement device is configured to capture the at least one differential output signal.

Described examples include an integrated circuit including a receive portion to receive an encoded transmission on a line. The receive portion has: a wake mode in which the receiver is capable of receiving the encoded transmission; and a sleep mode in which the receiver is not capable of receiving the encoded transmission. A wakeup controller monitors the line for a wakeup signal and provides a signal to the receive portion to cause the receive portion to enter the wake mode when the wakeup controller receives the wakeup signal.

A system for using different scan chains to test differential circuit and a method thereof are disclosed. In the system, two scan chains are set up for two electronic components on a target circuit board, and test data for the two scan chains are sequentially pushed to the two scan chains respectively according to a data flow direction between the two scan chains, and after the electronic components output result data, a test result can be determined according to the test data for the two scan chains and the result data. This testing manner can be performed on all electronic components, so as to achieve the technical effect of stably performing differential signal test on all electronic components of the target circuit board.

Described examples include an integrated circuit including a receive portion to receive an encoded transmission on a line. The receive portion has: a wake mode in which the receiver is capable of receiving the encoded transmission; and a sleep mode in which the receiver is not capable of receiving the encoded transmission. A wakeup controller monitors the line for a wakeup signal and provides a signal to the receive portion to cause the receive portion to enter the wake mode when the wakeup controller receives the wakeup signal.

A processor includes a transmitter to transmit, to a receiver, a differential pair of signals including a positive signal transmitted across a positive conductor and a negative signal transmitted across a negative conductor. A first programmable analog delay circuit is coupled to the positive conductor to provide a first delay to the positive signal and a second programmable analog delay circuit is coupled to the negative conductor to provide a second delay to the negative signal. A controller receives data based on a bit error rate (BER) of the differential pair of signals as measured by a bit error checker of the receiver. In response to determining the BER is less than a threshold BER, the controller stores a first delay value to program the first delay and store a second delay value to program the second delay.

The present invention discloses a differential signal skew detecting circuit configured to detect a skew of a differential signal. An embodiment of the circuit includes: a common mode voltage outputting circuit configured to output a common mode reference voltage and a common mode skew voltage; and a skew detecting circuit configured to inspect the common mode reference voltage and the common mode skew voltage according to a clock signal so as to output a skew detection value, in which when the skew detecting circuit detects the skew of the differential signal, the skew detection value is a first value, and when the skew detecting circuit detects no skew of the differential signal, the skew detection value is a second value.