An integrated circuit die includes a core fabric configurable to include an aging measurement circuit and a device manager coupled to the core fabric to operate the aging measurement circuit for a select period of time. The aging measurement circuit includes a counter to count transitions of a signal propagating through the aging measurement circuit during the select period of time when the aging measurement circuit is operating. The transitions of the signal counted by the counter during the select period of time are a measure of an aging characteristic of the integrated circuit die.

Disclosed is a capability test method based on a joint test support platform. The method includes steps of describing an initial capability in a test, combining a capability to be developed based on the initial capability, and determining an evaluation strategy and a joint task background information of the test. Further, the method includes generating a logical shooting range for the joint test support platform according to the joint task background information, developing a test scenario according to the joint task background information and the logical shooting range, decomposing the test scenario, determining a test plan corresponding to the test scenario, executing the test according to the test plan, analyzing and evaluating a test result of the test, and generating one or more joint capability evaluation reports for the test.

A method includes mapping an aging measurement circuit (AMC) into the core fabric of an FPGA and operating the AMC for a select time period. During the select period of time, the AMC counts transition of a signal propagating through the AMC. Timing information based on the counted transitions is stored in a timing model in a memory. The timing information represents an aging characteristic of the core fabric at a time that the AMC is operated. An EDA toolchain uses the timing information in the timing model to generate a timing guard-band for the configurable IC die. The AMC is removed from the core fabric and another circuit device is mapped and fitted into the core fabric using the generated timing guard-band models. The circuit device is operated in the configurable IC die based on the timing guard-band models.

A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.

Methods and systems for performing fault injection testing on an integrated circuit hardware design. The methods include: (a) receiving a raw fault node list identifying one or more fault nodes of the hardware design; (b) receiving information indicating a grouping of the fault nodes in the raw fault node list into a plurality of fault node groups, each fault node group comprising fault nodes that have a same effect on a failure mode of the hardware design; (c) generating a final fault node list based on the fault node groups; (d) selecting a set of fault injection parameters from the final fault node list, the set of fault injection parameters identifying at least one fault node in the final fault node list to fault; (e) performing a fault injection test on the hardware design by causing a fault to be injected into a simulation of the hardware design based on the selected set of fault injection parameters; (f) determining a result of the fault injection test; (g) storing the result of the fault injection test; and repeating (d) to (g) at least once.

In certain aspects, a pattern generation system includes a pattern generator, a memory, a pin function register, a pin function mapper, and a set of source selectors. The pattern generator generates a plurality of source patterns. The memory stores a lookup table set. The lookup table set describes a mapping relationship between the plurality of source patterns and a set of test channels, and is indexed based on a pin function index. The pin function register stores a value of the pin function index. The pin function mapper executes a pin-mapping operation to generate a set of source selection signals based on the value of the pin function index and the lookup table set. Each source selector selects and outputs a source signal from the plurality of source patterns to a corresponding test channel based on a corresponding source selection signal received from the pin function mapper.

A first circuit outputs a third signal having a first level during a period over which first and second signals have the same level, and having a second level during a period over which the first and second signals have different levels. A second circuit outputs a fifth signal having the first level during a period over which a fourth signal having the same level as the third signal has the same level as the first signal, and having the second level during a period over which the first and fourth signals have different levels. A third circuit outputs a sixth signal having a third level during a period over which the second and fifth signals have the same level, and having a fourth level during a period over which the second and fifth signals have different levels.

Embodiments are directed to a computer implemented method and system for the testing, characterization and diagnostics of integrated circuits. A system might include a device under test, such as an integrated circuit, that includes an adaptive microcontroller. The method includes loading a testing program for execution by the adaptive microcontroller, causing the microcontroller to execute the testing program. Once results from the testing program are received, the testing program can be adaptively modified based on the results. The modified testing program can be run again. The testing program can modify parameters of the integrated circuit that are not externally accessible. Other embodiments are also disclosed.

According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.

Systems and methods for predicting the trajectory of an object are disclosed herein. One embodiment receives sensor data that includes a location of the object in an environment of the object; accesses a location-specific latent map, the location-specific latent map having been learned together with a neural-network-based trajectory predictor during a training phase, wherein the neural-network-based trajectory predictor is deployed in a robot; inputs, to the neural-network-based trajectory predictor, the location of the object and the location-specific latent map, the location-specific latent map providing, to the neural-network-based trajectory predictor, a set of location-specific biases regarding the environment of the object; and outputs, from the neural-network-based trajectory predictor, a predicted trajectory of the object.