A test and measurement system for parallel waveform analysis acquires waveforms resulting from performing tests on a device under test (DUT) and performs, at least partially in parallel, respective analyses of the waveforms resulting from performing tests on the DUT. The system also acquires a first waveform resulting from performing a first test with an oscilloscope on a DUT and performs analysis of the first waveform at least partially in parallel with acquiring a second waveform. Additionally, the system tracks a plurality of testing assets using inventory information of a plurality of testing equipment on the network and enables remote users to access equipment logs and results of the respective analyses of the waveforms stored on a cloud computing system for performance of analytics.

A system for data creation, storage, analysis, and training while margin testing includes a margin test generator coupled through an interface to a Device Under Test (DUT). The margin test generator is structured to modify test signals for testing the DUT during one or more testing states of a test session to create testing results. The testing results are stored in a data repository along with a DUT identifier of the DUT tested during the test session. A comparator determine whether any results of the DUT test results match a predictive outcome that is based from an analysis of previous DUT tests. If so, a message generator produces an indication that the tested DUT matched the predictive outcome.

An apparatus for determining a single decision function is configured to obtain measurements from a plurality of devices under test corresponding to stimulating signals applied to the plurality of devices under test. The stimulating signals correspond to a set of tests performed on the plurality of devices under test. The apparatus may further determine a subset of tests from the set of tests, such that the subset of tests is relevant for indicating whether the plurality of devices under test pass the set of tests. The apparatus may also determine the single decision function applicable to measurements from an additional device under test tested using the subset of tests, such that the single decision function is adapted to predict a test result for the set of tests on the basis of the subset of tests.

A method and device for detecting a malicious circuit on an integrated circuit (IC) device is provided. The method includes generating a plurality of test patterns on the IC. A scan test circuit and the plurality of test patterns are used to test don't care bits of a function under test on the integrated circuit. Scan out data from the scan test circuit is provided in response to the plurality of test patterns. The scan out data is stored in a memory on the integrated circuit. The scan out data is monitored over a predetermined time period. If it is determined that a characteristic of the scan out data has changed within the predetermined time period, an indication that a malicious circuit has been detected is output. The device includes circuitry for performing the method in the field.

A semiconductor or integrated circuit block including a sense node and a converter circuit, in which the sense node develops a low frequency electrical parameter that is constant or varies at a frequency below a predetermined frequency level, and in which the converter circuit converts the low frequency electrical parameter into an alternating electrical parameter having a frequency at or above the predetermined frequency level sufficient to modulate a laser beam focused within a laser probe area of the converter circuit. The converter may include a ring oscillator, a switch circuit controlled by a clock enable signal, a capacitor having a charge rate based on the low frequency electrical parameter, etc. The laser probe area has a frequency level based on a level of the low frequency electrical parameter to modulate the reflected laser beam for measurement of the electrical parameter by a laser voltage probe test system.

A failure diagnostic apparatus includes a path calculation unit which calculates, for each input pattern to a diagnosis target cell, a path affecting an output value of the diagnosis target cell when a failure is assumed as an activation path, a path classification unit which classifies the activation path associated with the input pattern for which the diagnosis target cell has passed a test and the activation path associated with the input pattern for which the diagnosis target cell has failed the test, a path narrowing unit which calculates a first failure candidate path, a second failure candidate path and a normal path of the diagnosis target cell based on classified activation paths, and a result output unit which outputs information on the first failure candidate path, the second failure candidate path and the normal path.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. Presented embodiments enable efficient and effective random generation of test input information. In one embodiment a method includes accessing a plurality of data values to write to a DUT, generating a plurality of addresses pseudo randomly and assigning the address to a respective one of the data values, wherein assignments of a particular address to different respective ones of the data values are randomly repeatable; and directing writing of the data values to the DUT in accordance with the plurality of addresses that are randomly generated and randomly repeated. The generating a plurality of addresses randomly can include normalization. Generating a plurality of addresses pseudo randomly and assigning the address to a respective one of the data values can include performing a confirmation check. The confirmation check can include checking if the addresses within proper parameters.

A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.

A first circuit outputs a third signal having a first level during a period over which first and second signals have the same level, and having a second level during a period over which the first and second signals have different levels. A second circuit outputs a fifth signal having the first level during a period over which a fourth signal having the same level as the third signal has the same level as the first signal, and having the second level during a period over which the first and fourth signals have different levels. A third circuit outputs a sixth signal having a third level during a period over which the second and fifth signals have the same level, and having a fourth level during a period over which the second and fifth signals have different levels.

An integrated circuit of an embodiment includes: a logic circuit; and a switch circuit, the logic circuit including: a first memory; a look-up table circuit having a first output terminal; a first selection circuit having a first input terminal connecting to the first output terminal, a second input terminal receiving scan input data, and a second output terminal, the first selection circuit selecting one of the first and second input terminals and connect the selected one to the second output terminal; a flip-flop having a third input terminal connected to the second and third output terminals; and a second selection circuit having a fourth and fifth input terminals connected to the third output terminal and the first output terminal respectively, and a fourth output terminal, the second selection circuit selecting one of the fourth and fifth input terminals and connect the selected one to the fourth output terminal.