Method and apparatus to test an integrated circuit includes retrieving power distribution data relating to an integrated circuit and designating a segment that includes at least one component of the integrated circuit. A switching limit associated with the segment may be set based on the power distribution data. Processes further generate a testing pattern that includes the determined switching limit associated with the segment.

An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.

According to an embodiment, a testing mechanism determines a status of circuits within a chip by analyzing fail signatures on a by-level basis to identify a high probability defect area within the chip. The testing mechanism further determines a whether functionally needed circuitry of the chip intersects with the high probability defect area within the chip and determines the status of the circuits in response to the determining of whether the functionally needed circuitry intersects with the high probability defect area.

Embodiments are directed to a computer implemented method and system for the testing, characterization and diagnostics of integrated circuits. A system might include a device under test, such as an integrated circuit, that includes an adaptive microcontroller. The method includes loading a testing program for execution by the adaptive microcontroller, causing the microcontroller to execute the testing program. Once results from the testing program are received, the testing program can be adaptively modified based on the results. The modified testing program can be run again. The testing program can modify parameters of the integrated circuit that are not externally accessible. Other embodiments are also disclosed.

Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

A semiconductor or integrated circuit block including a sense node and a converter circuit, in which the sense node develops a low frequency electrical parameter that is constant or varies at a frequency below a predetermined frequency level, and in which the converter circuit converts the low frequency electrical parameter into an alternating electrical parameter having a frequency at or above the predetermined frequency level sufficient to modulate a laser beam focused within a laser probe area of the converter circuit. The converter may include a ring oscillator, a switch circuit controlled by a clock enable signal, a capacitor having a charge rate based on the low frequency electrical parameter, etc. The laser probe area has a frequency level based on a level of the low frequency electrical parameter to modulate the reflected laser beam for measurement of the electrical parameter by a laser voltage probe test system.

A system for testing complex integrated circuits in the field using updated tests, test sequences, models, and test conditions such as voltage and clock frequencies, over the life cycle of the circuit.

Method and apparatus to test an integrated circuit includes retrieving power distribution data relating to an integrated circuit and designating a segment that includes at least one component of the integrated circuit. A switching limit associated with the segment may be set based on the power distribution data. Processes further generate a testing pattern that includes the determined switching limit associated with the segment.

The present invention has a first step for inputting an inspection signal having a predetermined pattern simultaneously to a plurality of devices connected in parallel to a tester and starting inspection having a predetermined pattern, a second step for determining whether a non-passing device is included in the predetermined pattern, a third step for sequentially executing a predetermined pattern and determining passing/non-passing (PASS/FAIL) status for each of the plurality of devices when it is determined in the second step that a non-passing device is included, and a fourth step for excluding a device determined as non-passing in the third step, subsequent inspection being performed for the devices other than the excluded device.

Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.