Aspects of the invention include a phase rotator, that is located at a built-in self-test (BIST) path of a receiver, receiving a clock signal from an on-chip clock. The phase rotator shifts the phases of the clock signal. The phase rotator transmits the shifted clock signal to a binary sequence generator, that is located at the receiver. The binary sequence generator outputs a binary sequence, where the binary sequence generator is driven by the shifted clock signal.

Introduced herein is a technique that reliably measures on-die noise of logic in a chip. The introduced technique places a noise measurement system in partitions of the chip that are expected to cause the most noise. The introduced technique utilizes a continuous free-running clock that feeds functional frequency to the noise measurement circuit throughout the noise measurement scan test. This allows the noise measurement circuit to measure the voltage noise of the logic during a shift phase, which was not possible in the conventional noise measurement method. Also, by being able to measure the voltage noise during a shift phase and hence in both phases of the scan test, the introduced technique can perform a more comprehensive noise measurement not only during ATE testing but as part of IST in the field.

The present invention relates to a method for training a signal characterization neural network. The method comprises the steps of: providing a measurement signal having at least one distortion; assigning at least one predefined signal integrity identifier to a corresponding distortion within the measurement signal; generating at least one input training vector based on the provided measurement signal and the corresponding assigned signal integrity identifier; and applying the generated input training vector on input terminals of the signal characterization neural network for training the signal characterization neural network. The present invention also relates to a method for automatically characterizing a measurement signal. The present invention further relates to a measurement apparatus and a corresponding method for analyzing a waveform signal.

A test and measurement device has a port to receive a signal from a device under test (DUT), one or more analog-to-digital converters (ADC) to digitize the signal to create one or more waveforms, a display, and one or more processors configured to execute code that causes the one or more processors to: generate a histogram from the waveform, the histogram having one or more dimensions; and calculate one or more entropy values for each of the one or more dimensions. A method includes receiving a signal from a device under test (DUT) at a test and measurement device, digitizing the signal using one or more analog-to-digital converters (ADC) to produce a waveform, generating a histogram from the waveform, the histogram having one or more dimensions, and calculating one or more entropy values for each of the one or more dimensions,.

A measurement task is selected, where the measurement task is associated with a transmission of an encoded signal transmitted via a plurality of data lines. The encoded signal is encoded using one or more of 3-Phase, N-Phase, or N-factorial low-voltage differential signaling (LVDS) where N is at least three (3). A repeating waveform is generated corresponding to the measurement task. The repeating waveform corresponding to the measurement task is then transmitted via the plurality of data lines.

A technique for testing an electronic UUT by a test apparatus includes obtaining multiple DFTs of a test signal received from the UUT with the test apparatus configured differently for obtaining each DFT. The resulting DFTs include both valid content representing the test signal and invalid content introduced by the test apparatus. The improved technique suppresses the invalid content by generating a corrected DFT, which provides minimum magnitude values for corresponding frequencies relative to the test signal across the multiple DFTs.

A chip testing method includes: a data receiving window corresponding to each chip to be tested is determined; a time adjustment parameter corresponding to each chip to be tested is determined according to the data receiving window corresponding to each chip to be tested and a data input window preset for a test machine is determined; an actual input time point corresponding to each chip to be tested is determined according to the time adjustment parameter corresponding to each chip to be tested; and data is inputted to each chip to be tested at the actual input time point corresponding to the each chip to be tested, to enable each chip to be tested to receive the data inputted by the test machine in the data receiving window corresponding to the each chip to be tested.

A probe apparatus includes a tester including a voltage supply, and a probe card including a first probe and a first sensing pin. The first probe is electrically connected to both an output port of the voltage supply and an electrode pad of a first semiconductor device. The first sensing pin is electrically connected to both a controller and a sensing pad of the first semiconductor device.

A system for capturing an eye diagram is disclosed. In various embodiments, the system includes: a delay line arranged to receive a digital signal and output a time delayed version of the digital signal; an edge detection circuit arranged to receive the digital signal and the time delayed version of the digital signal, the edge detection circuit operating to output a signal corresponding to a logical value of the digital signal received coincident with an edge of the time delay version of the digital signal; a voltage comparator arranged to receive the digital signal and a reference voltage, the voltage comparator operating to output a first signal when a voltage of the digital signal and the reference voltage are equal to each other; and a controller that includes: an edge detection circuit receiver connected to receive the output signal from the edge detection circuit; a delay line control circuit connected to provide a delay time control signal to the delay line; a voltage comparator receiver connected to receive the first signal from the voltage comparator; and a voltage control unit connected to provide a controlled voltage to the voltage comparator.

A tester including an interface configured to interface with an electronic device and a logic circuit. The logic circuit includes a pattern generator and at least one finite-state machine and is configured to sequentially acquire read data from the electronic device at sequential testing points of a testing range for evaluating an operating parameter of the electronic device or the tester until a set of consecutive passing points having a first passing point and a last passing point is identified, in response to identifying the first passing point, write data within the logic circuit of the tester identifying the first passing point, in response to identifying the second passing point, write data within the logic circuit of the tester identifying the second passing point, and output only data identifying the first passing point and data identifying the last passing point to a software application.