A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

The present invention relates to a processing of a signal under test in order to compensate frequency variations in the signal under test. For this purpose, the signal under test is mixed with a further digital signal. A frequency of the further signal which is used for mixing with the signal under test may be adapted in real-time according to frequency variations in the signal under test.

A test and measurement instrument includes an input to receive a non-return-to-zero (NRZ) waveform signal from a device under test, a ramp generator to use the NRZ waveform signal to generate a ramp sweep signal, a gate to gate the ramp sweep signal and the NRZ waveform signal to produce gated X-axis and Y-axis data, and a display to display the gated X-axis and Y-axis data as a cyclic loop image. A method of generating a cyclic loop image includes receiving an input waveform, using the input waveform to generate a ramp sweep signal, gating the ramp sweep signal and the input waveform to produce gated X-axis and Y-axis data, and displaying the gated X-axis and Y-axis data as a cyclic loop image.

A system includes an input to receive a digital waveform signal, a memory, and one or more processors configured to execute code to cause the one or more processors to: generate a horizontal ramp sweep signal based on the digital waveform signal; receive a selection input to identify a segment of the digital waveform signal; gate the horizontal ramp sweep signal and the digital waveform signal based on the selection input to produce cyclic loop image data for the segment of the digital waveform; store the cyclic loop image data in the memory; and provide the cyclic loop image data as one or more inputs into a machine learning system. A method of waveform classification using a cyclic loop image includes receiving an input waveform, receiving a selection of a segment of the input waveform, transforming the segment of the input waveform into cyclic loop image data, the transforming comprising generating a horizontal ramp sweep signal based on edge transitions in the input waveform, and storing the cyclic loop image data in a memory; and sending the cyclic loop image data to a machine learning system to determine an attribute of the input waveform.

An apparatus for determining a single decision function is configured to obtain measurements from a plurality of devices under test corresponding to stimulating signals applied to the plurality of devices under test. The stimulating signals correspond to a set of tests performed on the plurality of devices under test. The apparatus may further determine a subset of tests from the set of tests, such that the subset of tests is relevant for indicating whether the plurality of devices under test pass the set of tests. The apparatus may also determine the single decision function applicable to measurements from an additional device under test tested using the subset of tests, such that the single decision function is adapted to predict a test result for the set of tests on the basis of the subset of tests.

A glitch detection circuit includes a first P-type field-effect transistor and a second P-type field-effect transistor which are biased by the same current, and a channel width-to-length ratio of the first P-type field-effect transistor is higher than that of the second P-type field-effect transistor. A capacitor having a terminal grounded and another terminal connected to the gates of the first and second P-type field-effect transistors and a power supply terminal. A determination circuit configured to determine that a negative glitch occurs when a voltage decreasing amount of the drain of the first P-type field-effect transistor is greater than that of the second P-type field-effect transistor, and determine that a positive glitch occurs when an voltage increasing amount of the drain of the second P-type field-effect transistor is greater than that of the first P-type field-effect transistor.

An interference detection device and a detection sensitivity adjusting method are provided. A signal generating circuit generates a detection signal. A delay circuit delays the detection signal to generate a plurality of delay signals with different delay time. A decision circuit selects one of the delay signals according to a first section signal for comparing with the detection signal to generate an interference detection result, where the delay signals are used for adjusting the detection sensitivity of the interference detection device.

A method for testing a circuit includes receiving, by a noise injection circuit, an input signal and generating a noise pulse. Generating the noise pulse includes computing an input resistor pulse, and computing an output resistor pulse. Generating the noise pulse further includes short-circuiting an output resistor substantially simultaneously with opening an input resistor. The method for testing the circuit includes modifying, by the noise injection circuit, the input signal using the noise pulse.

A signal analyzer for analyzing a signal comprises a frontend with at least two interleaved digitizers configured to digitize an input signal, thereby generating a digitized input signal. The signal analyzer also comprises a first interleave alignment filter established by a hardware interleave alignment filter that is configured to hardware-compensate non-ideal effects of the frontend in the digitized input signal in real-time, thereby generating a hardware-compensated, digitized input signal. Further, the signal analyzer comprises an acquisition memory configured to store the hardware-compensated, digitized input signal, thereby acquiring an acquired signal. Moreover, the signal analyzer comprises a second interleave alignment filter configured to fine-compensate further non-ideal effects of the frontend in a post-processing of the acquired signal. In addition, a method of analyzing a signal is described.

A noise source monitoring apparatus includes: a first storage unit storing captured image data; a second storage unit storing observed waveform data; a processing unit calculating, for each of the switch units, the degree of correlation between occurrence of a noise and operation of the switch unit, based on the captured image data and the observed waveform data; and a display control unit causing a display unit to display information indicating the degree of correlation.