An example integrated circuit (IC) die in a multi-die IC package, the multi-die IC package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS), is described. The IC die includes a Joint Test Action Group (JTAG) controller having a JTAG interface that includes a TDI, a TDO, a TCK, and a TMS, a first output coupled to first routing in the multi-die IC package, a first input coupled to the first routing or to second routing in the multi-die IC package, a master return path coupled to the first input, and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller, and selectively couple, in response to a first control signal, the TDO of the TAP to either the master return path or the TDO.

Techniques to perform semiconductor testing are described. Test equipment may test a chiplet for compliance with a semiconductor specification. A test device may connect to a test package with a model chiplet and a device under test (DUT) chiplet. The model chiplet may comprise a known good model (KGM) of the semiconductor specification. The test device may use the model chiplet to test the DUT chiplet. Other embodiments are described and claimed.

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

A method and an apparatus for reducing an effect of local process variations of a digital circuit on a hardware performance monitor includes measuring a set of performance values (c.sub.1, c.sub.2 . . . c.sub.n) of the digital circuit by n identical hardware performance monitors, where n is a natural number greater than 1, determining an average value c.sub.mean of the measured performance values (c.sub.1, c.sub.2 . . . c.sub.n), as an approximation of an ideal performance value c.sub.0, selecting one performance value c.sub.j of the set of performance values (c.sub.1, c.sub.2 . . . c.sub.n) by a controller, comparing the performance value c.sub.j with a reference value c.sub.ref by a controller the controller, resulting in a deviation value Δc, and controlling an actuator by using the deviation Δc for regulating the local global process variations to the approximation c.sub.mean of the ideal performance value c.sub.0.

A checking apparatus can test at least one first closed-loop control unit. The checking apparatus can include a first timing transmission unit which can generate a first periodic timing signal from a first time signal, and which can output the first periodic timing signal to a first PLL. The check device can further include a first oscillator which can generate a second periodic timing signal and which can output the second periodic timing signal to a second PLL. The checking device can additionally include a first clock, and can forward a first clock signal to a first input/output unit, and/or to a first computation unit. A first changeover signal can be used to control a first multiplexer such that depending on a state of the first changeover signal, the first multiplexer can forward either a first frequency-stabilized timing signal or a second frequency-stabilized timing signal to the first clock.

A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

According to one embodiment, a design support device executes a first processing. The first processing includes setting a control value group for a semiconductor element. The semiconductor element includes gates including first and second gates. The control value group includes a first time difference between first and second timings. A voltage is applied to the first gate at the first timing. A voltage is applied to the second gate at the second timing. The first processing includes calculating a characteristic value from an output result when an electrical signal corresponding to the control value group is input to the semiconductor element. The first processing includes calculating a first function from history data including not less than one data set. The data set includes the control value group and a score based on the characteristic value. The design support device sets a new control value group.

A system-on-chip includes a first scan register being in a first core and being closest to an input port of the first core; an inverting circuit on a feedback path of the first scan register; a second scan register in the first core; and a logic circuit on a data path between the first scan register and the second scan register. In a test mode for an AT-SPEED test of the logic circuit, the inverting circuit generates test data by inverting scan data that are output from the first scan register, the first scan register stores the test data in response to a first pulse of a clock signal, the logic circuit generates result data based on the test data that are output from the first scan register, and the second scan register stores the result data in response to a second pulse of the clock signal.

An automated test equipment for testing one or more devices under test comprising a plurality of port processing units, comprising at least a respective buffer memory, and a respective high-speed-input-output, HSIO, interface for connecting with at least one of the devices under test. The port processing units are configured to receive data, store the received data in the respective buffer memory, and provide the data stored in the respective buffer memory to one or more of the connected devices under test via the respective HSIO interface for testing the one or more connected devices under test. A method and computer program for automated testing of one or more devices under test are also described.

An automated test equipment for testing a device under test comprises an on-chip-system-test controller. The on-chip system test controller comprises at least one debug interface or control interface configured to communicate with the device under test. The on-chip-system-test controller optionally comprises at least one high bandwidth interface configured to communicate with the device under test. The on-chip-system-test controller is configured to control a test of a device-under-test which is a system-on-a chip.