A measurement device with automatic optimization capabilities comprises at least one signal processing component with a physical detector and a virtual detector component comprising at least one virtual detector for a signal processing component without physical detector. The physical detector is configured to physically measure a measurement value assigned to the signal processing component. The virtual detector component is configured to use a model of a signal processing chain from the physical detector to the location of the virtual detector. The model comprises at least one model parameter for the signal processing chain. The measurement device is configured to adapt the virtual detector component with respect to a measurement type for the signal to be measured. The virtual detector component is configured to use the model and the at least one measurement value. The virtual detector component is configured to determine a virtually determined value based on the model and the at least one measurement value. The measurement device is configured to use the virtually determined value to determine a setting for the measurement device. In addition, a method of setting a measurement device is described.

A test override circuit includes a memory that includes multiple memory instances. A path selector receives a control signal from automatic test pattern generator equipment (ATE) to control data access to data paths that are operatively coupled between the memory instances and a plurality of logic endpoints. The path selector generates an output signal that indicates which of the data paths is selected in response to the control signal. A gating circuit enables the selected data paths to be accessed by at least one of the plurality of logic endpoints in response to the output signal from the path selector.

A circuit includes a multipath memory having multiple cells and a plurality of sequence generators. Each sequence generator of the plurality of sequence generators drives one separate cell of the multiple cells via an automatic test pattern generator (ATPG) mode signal for each cell. The ATPG mode signal for each cell is configured via a sequence configuration input that controls a timing sequence to test each cell. The state of the ATPG mode signal of each cell selects whether test data or functional data is output from the respective cell.

A method and apparatus for determining jitter, a storage medium and an electronic device are disclosed. The method for determining jitter includes: determining a plurality of measurement time points for an output signal from an integrated circuit (IC); identifying one or more jitter points from the plurality of measurement time points by comparing the output signal with a predetermined signal at the plurality of measurement time points; and determining a jitter of the output signal of the IC based on the one or more jitter points. The jitter of the output signal of an IC chip can be determined without relying on any other additional equipment.

A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.

A test override circuit includes a memory that includes multiple memory instances. A path selector receives a control signal from automatic test pattern generator equipment (ATE) to control data access to data paths that are operatively coupled between the memory instances and a plurality of logic endpoints. The path selector generates an output signal that indicates which of the data paths is selected in response to the control signal. A gating circuit enables the selected data paths to be accessed by at least one of the plurality of logic endpoints in response to the output signal from the path selector.

A test method for a semiconductor device includes: loading a test tray having semiconductor devices of first and second lots arranged thereon into a test chamber; storing lot information of each of the semiconductor devices; performing a test program on each of the semiconductor devices; obtaining ID information of each of the semiconductor devices; matching the ID information with the lot information to generate lot sorting information; and sorting the semiconductor devices based on results of the test program and the lot sorting information.

Apparatus for testing an integrated circuit is described, including a set of signal conductors for communicating signals to respective external conductors of the integrated circuit. The apparatus also includes a tester comprising circuitry for outputting a signal. An interposer is electrically coupled between the set of signal conductors and the tester. The interposer comprises circuitry for selecting a set of signals between the set of signal conductors and the tester and outputting the set of signals. A signal processing apparatus is coupled to receive the set of signals, and the signal processing apparatus is operable to evaluate a parameter associated with each signal in the set of signals.

A method of capturing instrument data using a communications device includes recognizing an action performed by a user on the communication device, one of either transmitting or receiving a trigger message between the communications device and at least one instrument, storing instrument data in a memory on the at least one instrument, and transmitting the instrument data and user information to a network. A test system includes a test and measurement device having at least one communications link, a memory, and a processor configured to execute instructions that cause the processor to receive a message through the communications link, save instrument data into the memory, and transmit the instrument data to a remote location; and a communications device having at least one communications link, a memory, and a processor configured to execute instructions that cause the processor to recognize an action performed by a user, send the message to the test and measurement device, store associated information including user information, and transmit the user information to the remote location.

A method for failed die clustering is provided that includes extracting a data set of failed die on a wafer from a wafer map for the wafer, determining a density parameter for clustering the failed die, removing false failures from the data set of failed die to generate a reduced data set of failed die, locating clusters of failed die in the reduced data set by executing a density-based spatial clustering of applications with noise (DBSCAN) algorithm with the density parameter, and applying a guard band to each located cluster.