An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for at least one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.

A system is provided for distributed execution of a sequence processing chain. The system comprises an interface adapted to set a measurement sequence for a plurality of measurement sites, each comprising a sequence runner. The system further comprises a sequencer repository adapted to be accessed locally from the plurality of measurement sites. Moreover, the system comprises a sequence state manager adapted to receive measurement sequence states from at least one sequence runner and further adapted to distribute the measurement sequence states to other sequence runners via a network. In this context, the measurement sequence states are associated with data and/or results through the sequence processing chain.

A method of circuit yield analysis for evaluating rare failure events includes performing initial sampling to detect failed samples respectively located at one or more failure regions in a multi-dimensional parametric space, generating a distribution of failed samples at discrete values along each dimension, identifying the failed samples, performing a transform to project the failed samples into all dimensions in a transform space, and classifying a type of failure region for each dimension in the parametric space.

Aspects of the invention include systems and methods directed to a portable chip tester. A non-limiting example of a system includes a housing, a printed circuit board mounted on the housing, in which the printed circuit board includes a first interface operable to permit electrical communication between the printed circuit board and a device under test. The system further includes a mount operable to enable an electrical connection with an integrated circuit, in which the integrated circuit is operable to manage testing the device under test under a testing protocol. The system further includes a power supply and a software platform that includes a memory having computer readable instructions and one or more processors for executing the computer readable instructions. The computer readable instructions controlling the processors to perform operations including directing the integrated circuit to manage testing of the device under test pursuant to the testing protocol.

A function verification method for a boundary scan test controller is disclosed. In the method, the configuration positions of input/output connectors on a test board correspond to configuration positions of to-be-verified connectors on a boundary scan test controller, so that when the test board is stacked and positioned on the boundary scan test controller, the input/output connectors can be electrically connected to the to-be-verified connectors corresponding thereto, respectively. After being electrically connected to the boundary scan test controller via a USB port, the test control host creates a test script according to information of the test board and all operations of the to-be-verified connectors, and then execute a test program in the to-be-verified connectors according to the test script, and generates a test report, and determines whether the boundary scan test controller meets shipment or production requirement according to the test report.

A method and a circuit for adaptive regulation of body bias voltages controlling nmos and pmos transistors of an integrated circuit includes a digital circuit, a counter, a control unit and a charge pump. A first ring oscillator monitor measures a period duration of nmos transistors and a second ring oscillator monitor measures a period duration of pmos transistors. A first closed control loop adaptively regulates the performance c.sub.n of the body bias controlled nmos transistors of the digital circuit by comparing the measured period duration of nmos dominated first ring oscillator monitor to a period duration of a reference clock and a second closed control loop adaptively regulating the performance c.sub.p of the body bias controlled pmos transistors of the digital circuit by comparing the measured period duration of pmos dominated second ring oscillator monitor to the period duration of the reference clock.

A method of identifying defects in an electronic assembly, comprising, by a processing unit, obtaining a grid of nodes representative of a location of electronic units of an electronic assembly, wherein each node is neighboured by at most eight other nodes, wherein a first plurality of nodes represents failed electronic units according to at least one test criterion, and a second plurality of nodes represents passing electronic units according to the least one first test criterion, based on the grid, determining at least one first and second straight lines, and attempting to connect the first and second straight lines into a new line, wherein if at least one node from the new line belongs to the second plurality of nodes, concluding that an electronic unit represented by the node on the grid is a failed electronic unit, thereby facilitating identification of a failed electronic unit on the substrate.

A computer-implemented method for testing a system for at least one requirement. The method includes: the requirement is received in machine-readable form, at least one first input variable is ascertained for the test of the system for the received requirement, a design of the system is simulated as a function of the ascertained first input variable, an output variable of the simulated system is ascertained and it is ascertained as a function of the output variable whether the system meets the requirement, it is checked whether the simulation meets a quality requirement, if the simulation meets the quality requirement and the system meets the requirement, it is checked whether a sufficient test coverage is reached for the requirement, if the sufficient test coverage for the requirement is reached, the test for the requirement is completed.

A non-transitory computer-readable recording medium has stored therein a program that causes a computer to execute a process, the process including: generating, based on search history information indicating history of search in a component search device with respect to feature values of a component, appearance frequency information indicating frequencies at which the feature values appear in the search history information; generating, based on the appearance frequency information, weighting information in which weights are associated with the feature values; executing learning on accumulated failure record information to build a failure estimation model for estimating a failure rate of the component; and estimating the failure rate of the component by using the built failure estimation model.

An integrated circuit method processes parametric data for each integrated circuit die in a plurality of integrated circuit die to determine an expected data pattern, screens integrated circuit die by comparing a data pattern corresponding to a plurality of parametric data for the integrated circuit die to an expected data pattern and, responsive to the comparing, determining whether a difference between the data pattern corresponding to a plurality of parametric data for the predetermined integrated circuit die and the expected data pattern is beyond a tolerance.