Embodiments herein describe techniques for binning integrated circuits (ICs) using an adaptive binning system that can re-bin the ICs in response to receiving a new or updated test specification. Unlike static binning systems, in one embodiment, the binning system receives measured test data from a testing system. Put differently, instead of a testing apparatus simply indicating whether an IC does (or does not) satisfy the criteria in the test specification, the testing apparatus provides measured test data to the binning system. The binning apparatus can then store the received test data. As such, if a new test specification is received or generated, the binning system can use the already saved test data to re-bin the ICs using the criteria in the new test specification without having to re-test the ICs. In this manner, the binning system can re-categorize the ICs as customer needs or customer demand changes.

A batch testing system includes a test device, a plurality of machines to be tested and a server. The test device writes a BIOS with a RMT test to each machine to be tested, and starts each machine to be tested to run the RMT test, and then each machine to be tested writes a test result to a specific storage location in a baseboard management controller thereof. When entering an operating system, each machine to be tested reads and analyzes the test result at the specific storage location to output an analysis result, and then transmits the analysis result to the server through a network. The server receives and counts the analysis results transmitted by the machines to be tested. Therefore, the batch testing system can deploy the RMT test, and no intervention from operators is required in the whole process, which is suitable for the production testing stage.

An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for at least one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.

Embodiments herein describe binning and placement techniques for assembling a multi-die device to improve yield when a customer requests a high performance feature from the device. For example, the multi-die device may include multiple dies that are interconnected to form a single device or package. In one embodiment, the multiple dies are the same semiconductor die (e.g., have the same circuit layout) which are disposed on a common interposer or stacked on each other. The multi-die device can then be attached to a printed circuit board (PCB). Although the dies in the multi-die device may each include the same feature (e.g., a PCIe interface, SerDes interface, transmitter, memory interface, etc.), the multi-die device is assembled so that not all of the dies have a feature that satisfies the high performance requested by the customer. That is, at least one of the die includes a lower performance feature.

A method for an improved characterization of standard cells in a circuit design process is disclosed. Adaptive body biasing is considered during the design process by using simulation results of a cell set, a data-set for performance of the cell set, and a data-set for a hardware performance for a slow, typical and fast circuit property. Static deviations in a supply voltage are considered by determining a reference performance of a cell and a reference hardware performance monitor value at a PVT corner. A virtual regulation and adapting of body bias voltages of the cell set is performed such that the reference performance of the cell or the reference hardware performance monitor value will be reached at each PVT corner and for compensating the static deviation in the supply voltage. The results are provided in a library file.

An apparatus and a method for generation and adaptive regulation of body bias voltages of an integrated circuit efficiently generates control voltages for active body biasing The apparatus includes a digital circuit, a counter, a control unit and at least one charge pump. The control unit and the digital circuit are connected in a closed control loop, and the digital circuit comprises at least one hardware performance monitor to monitor a timing of a body bias voltage. The control loop is formed by a control path comprising the at least one charge pump, the hardware performance monitor and the control unit. The charge pump is controllably connected to the control unit to adjust the charge pump for generation and adaptive regulation of the body bias voltage according to a timing frequency difference between an output signal of the hardware performance monitor and a reference clock signal.

A system for performing an automated test is disclosed. The method comprises receiving a plurality of work orders and a plurality of constraints for scheduling a plurality of tests on a plurality of DUTs using automated test equipment (ATE) available on a production floor, wherein the ATE comprises a plurality of test cells, and wherein each test cell comprises a plurality of testers and an automated handler. The method further comprises developing a test plan to execute the plurality of tests, wherein the test plan is customized in accordance with the information in the plurality of work orders and the plurality of constraints. Finally, the method comprises scheduling the plurality of tests to the plurality of test cells to maximize throughput of the plurality of DUTs.

A method for identifying outlier devices during testing, includes: establishing binning limits for a device being tested based on one or more rules generated from external test results data of tests involving similar devices; receiving test results data in real time for the device being tested while the device is on a device tester; applying the one or more rules to the test results data for the device in real time; determining in real time, based on results of applying the one or more rules to the test results data, whether the device is an outlier with respect to the binning limits; and in response to determining that the device is an outlier, binning the outlier device separately from tested devices having test results data falling within the binning limits.

In a method of circuit yield analysis, the method includes: detecting a plurality of failed samples respectively located at a plurality of failure regions in a multi-dimensional parametric space; clustering the failed samples to identify the failure regions; filtering features of the failed samples to determine a parameter component that is a non-principal component in affecting circuit yield; applying a dimensional reduction method on a dimension corresponding to the parameter component; and constructing a final importance sampling (IS) distribution function using a mixed Gaussian (mGaussian) function corresponding to all of the failure regions containing a rare failure event.

A non-transitory computer-readable recording medium has stored therein a program that causes a computer to execute a process, the process including: generating, based on search history information indicating history of search in a component search device with respect to feature values of a component, appearance frequency information indicating frequencies at which the feature values appear in the search history information; generating, based on the appearance frequency information, weighting information in which weights are associated with the feature values; executing learning on accumulated failure record information to build a failure estimation model for estimating a failure rate of the component; and estimating the failure rate of the component by using the built failure estimation model.