A voltage attack detection circuit includes: at least one voltage regulation circuit, where the at least one voltage regulation circuit is connected to an external supply respectively, the at least one voltage regulation circuit is configured to convert the external supply to at least one internal supply, and the at least one internal supply is configured to output at least one first voltage respectively; at least one voltage sensor, where the at least one voltage sensor is connected to the at least one internal supply respectively, so as to receive the at least one first voltage respectively, each voltage sensor of the at least one voltage sensor is configured to output a reference voltage based on a received reference voltage and a received first voltage, the reference voltage is configured to indicate whether a received first voltage is within a present voltage range.

Herein disclosed are an electronic component testing system and a time certification method. The electronic component testing system comprising a testing device and an interface device. The testing device comprises a backboard, and the backboard electrically connected to at least one test board and comprising a time certification component. The interface device, electrically connected to the testing device, provides a test instruction. Wherein the time certification component stores an authorization start time and an authorization end time. Wherein the testing device starts a test procedure according to the test instruction, the time certification component updates the authorization start time to a first stop time of the test procedure after the test procedure is completed.

An integrated circuit (IC) protection circuit can include a reconfigurable block that receives a seed value from a tamper-proof memory and generates a dynamic key; an authentication block that receives the dynamic key from the reconfigurable block and taint bits from a scan chain to generate an authentication signature; and an encryptor that encrypts a test pattern response on the scan chain if a mismatch is found between the authentication signature and a test pattern embedded signature.

An apparatus includes a daughter die (DD) logic, and an arbitrator connected to the DD logic, and connected to an external testing device and a main die (MD) included in a multi-chip package (MCP). The apparatus further includes an enable logic configured to receive a message from the MD, based on the received message, determine whether the MD or the external testing device is enabled to access the DD logic, and based on the external testing device being determined to be enabled to access the DD logic, control the arbitrator to enable the external testing device to access the DD logic.

Systems and techniques of the present disclosure may provide remote debugging of an integrated circuit (IC) device while preventing unauthorized access of device intellectual property (IP). A system may include an IC device that generates an encrypted session key and an interface that enables communication between the IC device and a remote debugging site. The interface may enable the IC device to send the encrypted the encrypted session key to initiate a remote debug process, receive an acknowledgement from the remote debugging session, and authenticate the acknowledgement. Further, the interface may enable to the IC device to initiate a secure debug session between the IC device and the remote debugging site.

An Integrated Circuit (IC) includes electronic circuitry, an electronic fuse (eFuse) and a protection circuit. The eFuse is configured to be selectably programmed to a logical state. The electronic circuitry is configured to read the eFuse and to operate in accordance with the logical state read from the eFuse. The eFuse has a first range of operational voltages, and the electronic circuitry has a second range of operational voltages that is broader than the first range of operational voltages. The protection circuit is configured to prevent the electronic circuitry from misreading the logical state of the eFuse due to a voltage supply to the IC falling within the second operational voltage range but outside the first operational voltage range.

An apparatus includes a daughter die (DD) logic, and an arbitrator connected to the DD logic, and connected to an external testing device and a main die (MD) included in a multi-chip package (MCP). The apparatus further includes an enable logic configured to receive a message from the MD, based on the received message, determine whether the MD or the external testing device is enabled to access the DD logic, and based on the external testing device being determined to be enabled to access the DD logic, control the arbitrator to enable the external testing device to access the DD logic.

Disclosed are methods, systems and devices for implementing built-in self-test (BIST) to be performed by an untrusted party and/or in an unsecure testing environment. In an embodiment, a test access port (TAP) on a device may enable a party to initiate execution of one or more BIST procedures on the device. Additionally, such a TAP may enable loading of encrypted instructions to be executed by one or more processors formed on a device under test.

A method for detecting at least one glitch in an electrical signal. This method comprises: generating, from said electrical signal, at least one digital oscillating signal which is sensitive to glitches; and—performing the following steps as a repeatable round: (a) assigning a time window to at least one digital oscillating signal; said time window being implemented on the basis of a clock signal substantially insensitive to said at least one glitch to be detected; (b) determining from said time window a sampling value of the digital oscillating signal, said sampling value being characteristic of said digital oscillating signal throughout its time window; (c) detecting any potential glitch in said electrical signal by comparing said sampling value with an expected reference value; and (d) outputting a response typifying a result of the comparison step. Also, a device for implementing said method is described.

A circuit includes a voltage comparator with an output, a first input and a second input, the first input being coupled to a first reference voltage terminal. An operational transconductance amplifier has an output coupled to the second input of the voltage comparator, an inverting input coupled to the output of the operational transconductance amplifier, and a non-inverting input coupled to a second reference voltage terminal. A filter capacitor is coupled in series between a power supply terminal and the second input of the voltage comparator.