Systems and methods for secure testing and debugging of electronic devices are described. In one embodiment, the systems and methods may include an electronic device that includes a control switch placed on a device test bus of the electronic device between a debugger external to the device and a debug interface on the device. In some cases, the device may include at least one register placed on the device test bus between the debugger and authentication logic of the electronic device.

A circuit includes a voltage comparator with an output, a first input and a second input, the first input being coupled to a first reference voltage terminal. An operational transconductance amplifier has an output coupled to the second input of the voltage comparator, an inverting input coupled to the output of the operational transconductance amplifier, and a non-inverting input coupled to a second reference voltage terminal. A filter capacitor is coupled in series between a power supply terminal and the second input of the voltage comparator.

A method includes in part, generating an electro-optical frequency map (EOFM) of an active layer of an integrated circuit (IC), retrieving a reference map of the IC, comparing the EOFM of the IC with the reference map to determine whether there is a match between an intensity of an identified region in the EOFM map and an intensity of a corresponding region of the reference map, and detecting one or more hardware trojans in the IC if there is no match. The reference map may be associated with a layout of an IC known not to include hardware trojans. The reference map also may be a second EOFM associated with the IC. Alternatively, the reference map may be generated by applying power to the IC, and applying a clock signal to the IC.

A method for protecting a mobile terminal device from cyber security threats, including the steps of: detecting that the mobile terminal device is successfully connected only through one or both of a selected physical serial interface connected to a device for facilitating the testing or a wired network interface, which is connected to an electrical utility device. Prior to executing a test routine by the mobile terminal device, switching the mobile terminal device to a test state by: disabling an internal firewall, disabling one or more remaining network interfaces and serial interfaces, such that existing communications or connections are terminated and new communications and connections are prevented. Enabling communication to one or both of the selected physical serial interface and the wired network interface, performing the testing on the at least one electrical utility device according to the executed test routines under control of the mobile terminal device until completion.

A sensor system includes a sensor having a charge storage device controllably connected to a voltage source under control of a signal under test; and a readout circuit coupled to the charge storage device to determine whether the pulse width of the signal under test has changed greater than a threshold amount according to a voltage at the charge storage device. In some cases, the determination of whether the pulse width of the signal under test has changed includes determining whether the voltage satisfies a condition with respect to a comparison voltage. In some cases, the determination of whether the pulse width of the signal under test has changed is based on a propagation delay through a delay chain, where the propagation delay is dependent on the voltage.

An example method for restricting read access to content in the component circuitry and securing data in the supply item is disclosed. The method identifies the status of a read command, and depending upon whether the status disabled or enabled, either blocks the accessing of encrypted data stored in the supply chip, or allows the accessing of the encrypted data stored in the supply chip.

A fully digital integrated circuit apparatus (200) and method (300) are provided for generating a test mode enable signal with a digital non-resettable state retention storage circuit (210) connected to store an authentication control pattern for authorizing test mode access to a secure circuit, a digital safety interlock gate circuit (220) connected to store a safety interlock gate setting that may be accessed independently from a test mode enable signal, and combinatorial logic circuitry (205) for generating the test mode enable signal only when the interlock safety gate setting is set to a first value and the digital non-resettable state retention storage circuit stores the authentication control code.

An integrated circuit (IC) includes functional logic therein that can be enabled by application of a predefined thermal cycle. The IC includes an enabling fuse operatively coupled to the functional logic, the functional logic being disabled unless enabled by activation of the enabling fuse. A set of thermal sensors are arranged in a physically distributed manner through at least a portion of the IC. A test control macro operatively couples to the set of thermal sensors and the enabling fuse for activating the enabling fuse to enable the functional logic in response to application of a thermal cycle that causes the set of thermal sensors to sequentially experience a thermal condition matching a thermal sequence enabling test. A related method and system for applying the predefined thermal cycle are also provided.

An example method for restricting read access to content in the component circuitry and securing data in the supply item is disclosed. The method identifies the status of a read command, and depending upon whether the status disabled or enabled, either blocks the accessing of encrypted data stored in the supply chip, or allows the accessing of the encrypted data stored in the supply chip.

Systems, apparatuses, and methods for implementing debug features on a secure coprocessor to handle communication and computation between a debug tool and a debug target are disclosed. A debug tool generates a graphical user interface (GUI) to display debug information to a user for help in debugging a debug target such as a system on chip (SoC). A secure coprocessor is embedded on the debug target, and the secure coprocessor receives debug requests generated by the debug tool. The secure coprocessor performs various computation tasks and/or other operations to prevent multiple round-trip messages being sent back and forth between the debug tool and the debug target. The secure coprocessor is able to access system memory and determine a status of a processor being tested even when the processor becomes unresponsive.