A method for diagnosing a bias power supply for an acquisition system including a matrix-array interface device having conductive rows and columns, each row being connected to an input port and to a bias power supply, each column being selectively connected to ground by controlling an output port, and at each intersection either a circuit or a shunt, connected between the intersected row and the intersected column, including the following steps: controlling an output port so as to ground a shunt, reading the input port corresponding to the shunt, a low state indicating a normal presence of the power supply, a high state indicating an abnormal absence.

An Automated Dynamic low voltage monitoring (LVM) based Low-Power (ADLLP) debug capability for a system-on-chip (SoC) as well as the open/closed-chassis platform for faster TTM (Time to Market) of the final platform or system. ADLLP Debug is achieved by detection of the probe connection between a target system (e.g., SoC) and debug host system. A user can dynamically override the power, clocks and LVM for intellectual property (IP) blocks not part of the debug trace by instructing a Power Management Controller (PMC) via the Inter Processor Communication (IPC) mailbox (or any other suitable mailbox driver) to set the registers in a Target Firmware (TFW) based on the probe and debug use-case.

Circuits, methods, and systems are provided which facilitate testing of asynchronous circuits having one or more global or local feedback loops. A circuit includes a data path and a scan path. The data path has an input configured to receive a data input signal, and a first output. The scan path includes a first multiplexer having a first input configured to receive the data input signal, a latch coupled to an output of the first multiplexer, a scan isolator coupled to an output of the latch, and a second multiplexer having a first input coupled to the first output of the data path and a second input coupled to an output of the scan isolator. The second multiplexer is configured to output a data output signal.

A system includes a power supply configured to adjust a voltage supplied to a device under test (DUT) based on one of an input voltage of the DUT supplied to a power supply sense input of the power supply and a feedback signal indicative of an internal voltage of the DUT supplied to the power supply sense input, and a relay circuit configured to transition between supplying the input voltage to the power supply sense input and supplying the feedback signal to the power supply sense input. When supplying the feedback signal to the power supply sense input, the relay circuit establishes an electrical path between the input voltage and the power supply sense input to prevent the power supply sense input from floating during the transition.

A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.

A chip testing circuit and a testing method thereof are provided. The chip testing circuit includes a parameter measurement circuit, a plurality of power supply circuits, a plurality of switch circuits, and a control circuit. The plurality of power supply circuits respectively provide power supply to a plurality of chips carried by a plurality of sockets. Each switch circuit is electrically connected between one socket and one power supply circuit. The control circuit is connected in parallel to a plurality of signal pins of the plurality of chips carried by the plurality of sockets, so that when the control circuit outputs test data, all the chips can simultaneously receive the test data. When executing a parametric test mode, the control circuit controls one of the switch circuits to be turned on and controls the parameter measurement circuit to perform an electrical performance test on the chips.

A power verification circuit is provided. The power verification circuit includes a current source, a resistive random access memory (RRAM) cell and a Zener diode. The current source is coupled to a power terminal. The RRAM cell is coupled between the current source and a ground terminal. The Zener diode has an anode coupled to the RRAM cell and a cathode coupled to the power terminal. The impedance of the RRAM cell is determined by the power voltage applied to the power terminal.

A circuit and a method for reducing interference of power on/off to hardware test. The circuit includes: a power unit, a voltage processing unit, a PSU and a to-be-tested hardware. An input terminal of the voltage processing unit is connected to the power unit, an output terminal of the voltage processing unit is connected to an input terminal of the PSU, and an output terminal of the PSU is connected to the to-be-tested hardware; the power unit is configured to provide an operating voltage; the voltage processing unit is configured to eliminate electric sparks caused by instability of the operating voltage at an instant of power on/off; the PSU is configured to convert a stable operating voltage outputted from the voltage processing unit into a direct current voltage required for the to-be-tested hardware; and the to-be-tested hardware is configured to receive the direct current voltage outputted from the PSU.

A circuit device is provided with a first codec including a first portion of a logic circuit and a second codec including a second portion of the logic circuit. The circuit device can also include a plurality of first scan chains coupled to the first codec and configured to shift a delayed test vector onto the first codec, wherein the delayed test vector is a test vector with a phase delay. A plurality of second scan chains can be coupled to the second codec and configured to shift the test vector onto the second codec.

According to one general aspect, an apparatus may include a first power signal having a high voltage. The apparatus may include a second power signal having a low voltage. The apparatus may include a third power signal having a voltage configured to switch between the high voltage and the low voltage. The apparatus may include a latching circuit powered by the first power signal and the second power signal. The apparatus may include a selection circuit configured to select between, at least, a first data signal and a second data signal, and powered by the first power signal, the second power signal, and the third power signal.