A power supply apparatus supplies a power supply voltage V.sub.DD. The power supply apparatus includes a compensation circuit in addition to a main power supply. The compensation circuit receives, via its input, as a feedback signal, a detection signal V.sub.S that corresponds to the power supply voltage V.sub.DD. The compensation circuit has input/output characteristics f.sub.IO that correspond to the characteristics of the main power supply and the characteristics of a target power supply to be emulated. The compensation circuit injects or otherwise draws a compensation current i.sub.COMP that corresponds to the detection signal V.sub.S to or otherwise from a node for generating the power supply voltage V.sub.DD.

A semiconductor device is capable of detecting a power supply voltage abnormality without degrading the performance of internal circuits. The semiconductor device includes a plurality of power supply inspection circuits and a result storage register. The power supply inspection circuits detect a power supply voltage abnormality in each pad that couples an internal wiring disposed in the semiconductor device to another part disposed outside of the semiconductor device. The result storage register stores inspection results indicated by result signals output from the power supply inspection circuits.

Aspects include techniques for implementing a clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry for encoding and correction of a chip. A computer-implemented method may include initializing a scan of the chip including data and a set of check bits protecting the data; applying a global control bit to a latch on the chip; and applying an additional clock to the latch so the check bits are updated using the on-chip circuitry.

A rechargeable power module (RPM) may include a rechargeable energy storage device such as a battery or capacitor, a charging circuit, a direct-current (DC) to DC converter, a low drop-out (LDO) voltage regulator and a controller. The charging circuit provides the rechargeable energy storage device with a charging current based on power requirements of device under test and the state of charge, or storage, of the energy storage device.

A method for testing a lifetime of a surface state carrier of a semiconductor, including the following steps, 1) a narrow pulse light source is used to emit a light pulse, and coupled to an interior of a near-field optical probe, and the near-field optical probe produces a photon-generated carrier on a surface of a semiconductor material under test through excitation. 2) The excited photon-generated carrier is concentrated on the surface of the semiconductor material, and recombination is conducted continuously with a surface state as a recombination center. 3) A change in a lattice constant is produced due to an electronic volume effect, a stress wave is produced, and a signal of the stress wave is detected in a high-frequency broadband ultrasonic testing mode. 4) Fitting calculation is conducted on the signal of the stress wave to obtain the lifetime of the surface state carrier τ.sub.c.

A test system is disclosed. The test system includes a tester, a first voltage stabilization circuit, and a device under test (DUT). The tester generates a first operational voltage and a control signal. The first voltage stabilization circuit transmits a second operational voltage, associated with the first operational voltage, to a socket board. The DUT operates with the second operational voltage received through the socket board. The first voltage stabilization circuit is further configured to control, according to the control signal, the second operational voltage to have a first voltage level when the DUT is operating.

In some embodiments, a system and/or method may test logic blocks for an integrated circuit. To alleviate problems associated with current methods of integrated circuit testing, a system may include a power switch control signal on a different voltage rail. In some embodiments, a Test VDD may be used to isolate the power switches from the rest of the logic cells in an integrated circuit. During testing, each logic block may be powered individually using the Test VDD to control the power switches to the logic blocks. When a logic block short is identified, the nonviable logic block may be isolated to such that the nonviable logic block is not used during the future and only viable logic blocks are used in the integrated circuit. This allows for use of logic within an integrated circuit that might otherwise have been discarded or destroyed because of one or more shorts.

An apparatus for providing a supply voltage to a device under test includes: a controlled source; a switchable resistor circuited between the output of the controlled source and a dut port, having a comparatively smaller first resistance in a first switch state and a second resistance in a second switch state; a regulator that provides a control signal to the controlled source, to regulate a voltage to be provided to the dut. The apparatus changes a switch state of the switchable resistor while a voltage is provided to the dut via the switchable resistor. The apparatus injects a compensation signal into a control loop including the regulator, the controlled source and the switchable resistor, to thereby cause a change of the voltage provided by the controlled source, to at least partially compensate a change of a voltage drop across the switchable resistor.

A circuit screening system includes a target circuit under test, a power circuit, and a clock generating circuit. The target circuit under test receives a first testing signal in a first period, and a second testing signal in a second period, and the first testing signal is different from the second testing signal. The power circuit provides a supply voltage to the target circuit under test, wherein a voltage level of the supply voltage maintains at a first voltage level in the first period, is pulled up to a second voltage level and back to the first level after the first period, and maintains at the first voltage level in a second period after the first period. The clock generating circuit provides a clock signal to the target circuit under test, wherein the clock signal has different profiles in the first period and the second period.

A first plurality of logic gates and a second plurality of logic gates may be associated with a symmetric configuration. A first output at a first value may be generated by the first plurality of logic gates based on a first portion of input signals. A second output may be generated by the second plurality of logic gates at the first value based on a second portion of the input signals. A subsequent first output at a particular value may be generated by the first plurality of logic gates based on a first portion of a second plurality of input signals and a subsequent second output may be generated by the second plurality of logic gates based on a second portion of the second plurality of input signals. A value of the subsequent second output may be complementary to the particular value of the subsequent first output.