This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

An integrated circuit includes a supply terminal to receive a supply voltage and a test terminal that operates in an input mode and an output mode. A test interface of the integrated circuit operates in a normal mode requiring a serial write to the test terminal to access test locations in the integrated circuit. The test interface also operates in an automatic mode in which addresses for test locations are auto incremented by toggling the supply voltage from a high voltage level to a low voltage level and back to the high voltage level. In an input mode, with the supply voltage at the low voltage level, the test pin receives configuration and address information. In output mode, with the supply voltage at the high voltage level, the test pin supplies test information corresponding to the address information received.

An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

A test apparatus for testing electrical parameters of a target chip, the apparatus including: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

An address register includes a plurality of edge-triggered flip-flop registers having an input D, an input R, an input CK, and an output Q; a counter logic; a shifter logic; a multiplexer; input ports including a reset signal RST, a clock signal CLK, a shift enable signal SE, a shift data input signal SI; an output port including address signals ADDR. D is coupled to a data output of the multiplexer; R is coupled to a reset (RST) pad; CK is coupled to a clock (CLK) pad; Q is coupled to an address (ADDR) pad; an input of the counter logic is coupled to ADDR; an input of the shifter logic is coupled to ADDR and the shift data input signal SI; an input of the multiplexer is coupled to SE, an output of the counter logic, and an output of the shifter logic.

A system comprises a memory sub-system controller mounted to a printed circuit board (PCB) and an in-circuit test (ICT) device. The memory sub-system controller has test points on the PCB comprising stimulus points and observation points. The ICT device connects to the test points of the controller. The ICT device converts automated test pattern generation (ATPG) input test vectors to test signals. A first set of pin drivers of the ICT device applies the test signals to the stimulus points of the controller and a second set of pin drivers of the ICT device read output signals output at the observation points of the controller. A comparator of the ICT device compares the output signals with output test vectors. The comparator provides test result data comprising a result of the comparison.

An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Resetting an integrated circuit (IC) by reset circuit of the IC comprises receiving a clock signal and a data signal. A sequence of bits of the data signal is stored in a memory based on the clock signal. A test mode signal is received and the sequence of bits is decoded in response to receiving the test mode signal. One of adjusting a counter value of a counter of the reset circuitry and outputting a reset signal corresponding to the counter value is performed based on the decoded sequence of bits.

The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies; and a benchmark circuit disposed adjacent to the scribe line and electrically coupled to a first conductive contact and a second conductive contact. The benchmark circuit includes a first device-under-test (DUT); a second DUT; a first switching circuit configured to selectively couple the first DUT and the second DUT to the first conductive contact; and a second switching circuit configured to selectively couple the first DUT and the second DUT to the second conductive contact.

A system is provided for distributed execution of a sequence processing chain. The system comprises an interface adapted to set a measurement sequence for a plurality of measurement sites, each comprising a sequence runner. The system further comprises a sequencer repository adapted to be accessed locally from the plurality of measurement sites. Moreover, the system comprises a sequence state manager adapted to receive measurement sequence states from at least one sequence runner and further adapted to distribute the measurement sequence states to other sequence runners via a network. In this context, the measurement sequence states are associated with data and/or results through the sequence processing chain.