An input selector for electrically connecting one of a plurality of test signals from a device under test to a test and measurement instrument includes a multiplexer having multiple inputs, each of the multiple inputs coupled to a different one of the plurality of test signals from the device under test, and having an output of a selected one of the multiple inputs, and an amplifier coupled to the output of the multiplexer for amplifying the selected test signal of the device under test before being sent as an output of the input selector to the test and measurement instrument. In alternative architectures, two or more amplifiers are coupled to the plurality of test signals, and the multiplexer selects an output of one of the two amplifiers to pass to a measurement instrument for testing.

In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.

The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.

An example apparatus includes a circuit and calibration circuitry. The circuit has complementary input ports to receive input signals including a monotonously rising and/or falling wave reference signal and a voltage-test signal to test at least one direct current (DC) voltage associated with the circuit by comparing the input signals using a first polarity and second polarity associated with the circuit to produce a first output signal and a second output signal. During operation, the circuit manifests an input voltage offset and a signal delay with each comparison of the input signals. The calibration circuitry processes the first and second output signals and, in response, calibrates or sets an adjustment for at least one signal path associated with the circuit in order to account for the input offset voltage and signal delay during normal operation of the circuit.

A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

Circuits, methods, and systems are provided which facilitate testing of asynchronous circuits having one or more global or local feedback loops. A circuit includes a data path and a scan path. The data path has an input configured to receive a data input signal, and a first output. The scan path includes a first multiplexer having a first input configured to receive the data input signal, a latch coupled to an output of the first multiplexer, a scan isolator coupled to an output of the latch, and a second multiplexer having a first input coupled to the first output of the data path and a second input coupled to an output of the scan isolator. The second multiplexer is configured to output a data output signal.

A semiconductor wafer and a multi-chip parallel testing method are provided. The semiconductor wafer includes a plurality of chips, a plurality of test pads, and a test control circuit. The test pads receive a plurality of test signals from a test fixture. The test control circuit is electrically connected to the chips and the test pads, selects at least one selected test signal from the test signals, generates a plurality of broadcast test signals according to the at least one selected test signal, and provides the broadcast test signals to the chips in parallel.

Described herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using a same scan chain compressor-decompressor circuit may be performed. Also disclosed herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using multiple different scan chain compressor-decompressor circuits may be performed.

Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.