A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.

A stack type semiconductor apparatus may be provided. The stack type semiconductor apparatus may include a plurality of semiconductor chips stacked and configured for transferring signals through through-hole vias. Each of the plurality of stacked semiconductor chips may include an error detection circuit configured to perform a down scan for transferring a signal to a lower direction and an up scan for transferring a signal to an upper direction through through-hole vias in a column direction among the through-hole vias, and to determine whether the through-hole vias have failed according to a down scan result value and an up scan result value.

A system and method for testing electronic circuit devices. The system has a central processing unit with a plurality of separate core processing units. The utility service program is initiated at the startup of the computer program which acts as an intermediary between user applications and the computer operating system. The utility service is responsive to an ATE execution engine to set an affinity for one or more processing cores for exclusive use for the ATE execution engine. The ATE execution engine communicates with the utility service to reserve one or more processing cores for execution of the program for testing electronic devices.

An unbalanced multiplexer and a scan flip-flop including the unbalanced multiplexer, wherein the unbalanced multiplexer includes a first transmission circuit transmitting a first input signal to an output terminal according to a logic state of a selection signal; and a second transmission circuit transmitting a second input signal to the output terminal according to the logic state of the selection signal. A delay characteristic of a first transmission path from a first input terminal to the output terminal along which the first input signal of the first transmission circuit is transmitted, and a delay characteristic of a second transmission path from a second input terminal to the output terminal along which the second input signal of the second transmission circuit is transmitted, are set differently.

An integrated circuit with functional circuitry and testing circuitry, the testing circuitry having a state machine operable in a plurality of different states. The integrated circuit also has a pin for receiving a signal, wherein the state machine is operable to transition between states in response to a change in level of the signal. Circuitry couples the signal of the pin, in a first level, to the state machine in a first time period for causing the state machine to enter a predetermined state, and circuitry maintains the signal in the first level to the state machine in a second time period for maintaining the state machine in the predetermined state. Also during the second time period, circuitry couples data received at the pin to a destination circuit other than the state machine, wherein the destination circuit is operable to perform plural successive scan tests using data from the pin without a power on reset of the functional circuitry.

The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.

Aspects include techniques for bypassing an encoded latch on a chip during a test-pattern scan and using on-chip circuitry to generate a desired encoded pattern, which is inserted into a scan-bypassed latch, to test the on-chip circuitry for defects. A computer-implemented method may include applying a global control bit to the chip; initializing a scan of the chip while bypassing the encoded latch; and applying an extra scan clock to initiate the encoded latch after completing the scan, wherein the encoded latch is updated with check bits generated by the on-chip circuitry.

Aspects include techniques for implementing a clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry for encoding and correction of a chip. A computer-implemented method may include initializing a scan of the chip including data and a set of check bits protecting the data; applying a global control bit to a latch on the chip; and applying an additional clock to the latch so the check bits are updated using the on-chip circuitry.

Embodiments include methods, and computer system, and computer program products for performing system functional test on a chip having partial-good portions. Aspects include: initializing, by system functional test software, a service engine of the chip, performing, by service engine, system functional test, and completing system functional test of chip. The chip may include service engine, a service engine memory and one or more “partial-good” portions. The initializing may include: loading system functional test software into the service engine memory, identifying each “partial-good” portion of the chip, writing a “partial-good” parameter for each “partial-good” portion of the chip identified to service engine memory, and triggering execution of system functional test. Method may include: decoding system functional test software, retrieving “partial-good” parameters, initializing “partial-good” portions of chip, and performing system functional test on “partial-good” portions of chip. The chip may include is a processor chip that has one or more “partial-good” cores.

The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.