This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

Embodiments are directed to a computer implemented method and system for the testing, characterization and diagnostics of integrated circuits. A system might include a device under test, such as an integrated circuit, that includes an adaptive microcontroller. The method includes loading a testing program for execution by the adaptive microcontroller, causing the microcontroller to execute the testing program. Once results from the testing program are received, the testing program can be adaptively modified based on the results. The modified testing program can be run again. The testing program can modify parameters of the integrated circuit that are not externally accessible. Other embodiments are also disclosed.

The present disclosure provides an electronic tester comprising at least one test fixture that couples to a device under test, at least one test instrument coupled to at least one of the test fixtures that measures signals in the device under test, a test controller that controls the device under test while the test is performed, and an adapter module comprising a general control interface that is coupled to the test controller, and a DUT-specific communication interface that couples to the device under test to communicate with the device under test, wherein the test controller controls the device under test with generic control signals sent to the general control interface, and wherein the adapter module translates the general control signals into DUT-specific control signals and transmit the DUT-specific control signals to the device under test. Further, the present disclosure provides a respective method.

A system for programming integrated circuit (IC) dies formed on a wafer includes a magnetic field transmitter that outputs a digital test program as a magnetic signal. At least one digital magnetic sensor (e.g., Hall effect sensor) is formed with the IC dies on the wafer. The digital magnetic sensor detects and receives the magnetic signal. A processor formed on the wafer converts the magnetic signal to the digital test program and the digital test program is stored in memory on the wafer in association with one of the IC dies. The magnetic field transmitter does not physically contact the dies, but can flood an entire surface of the wafer with the magnetic signal so that all of the IC dies are concurrently programmed with the digital test program.

A system and method to manage a single event latched (SEL) condition, the method including operations to monitor, for a predetermined condition associated with single event latched (SEL) states, a reset signal output from a watchdog device to a microprocessor, wherein the reset signal is responsive to a malfunction condition associated with the microprocessor. The method further includes operations to control provision of power to the microprocessor in response to detection of the predetermined condition.

A system with a self-test function has at least one system component which has at least one technical function, a fault simulation unit integrated in the system, a self-test unit integrated in the system, and a verification control unit integrated in the system, wherein the at least one system component is coupled to the fault simulation unit, wherein the fault simulation unit is designed to influence the operation of the system component to the effect that the at least one technical function is selectively impaired, wherein the self-test unit is designed to monitor operating parameters of the system component and to respectively generate a warning signal which indicates impairment of the respective at least one technical function, and wherein the verification control unit is designed to compare the warning signals generated by the self-test unit with expected warning signals on the basis of the impaired technical functions.

A test device and method with built-in self-test logic and a communication device. The test device includes at least one generator and at least one checker which are disposed between a physical layer and a medium access control layer. The at least one generator is configured to generate a protocol pattern to form a data path between the physical layer and the medium access control layer, and generate different pseudo random bit sequence patterns in the data path. The at least one checker is configured to test a data stream in the physical layer and/or the medium access control layer according to the pseudo random bit sequence patterns, thereby locating a fault position.

Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

A built-in self-test (BIST) circuit is disclosed which integrates the functions of pins for test input data TDI, test output data TDO and an analog input signal VPP into a single digital/analog input/output module, and internally produces a test trigger signal STROBE and a digital-analog conversion signal ANA. In addition, when there is a need to power the test chip with a voltage or current, a data generation circuit of the BIST circuit can generate a digital-analog conversion signal to change an operating mode of the digital/analog input/output module and hence enable the transmission of analog data. According to the present invention, the testing can be performed with only two pins, which leads to an improvement in test efficiency and a reduction in test cost.