An extended joint test action group based controller and a method of use allows easier testing of integrated circuits by reducing the power dissipation of an IC. The extended joint test action group (JTAG) controller tests internal storage elements that form digital units in an integrated circuit (IC) use a design for testing scan infrastructure on the IC, wherein the JTAG controller is extended by an overall reset generator for all digital units of the IC, and a finite state machine controls the overall reset generator. In reset mode the JTAG controller stops the at least one clock module in supplying the digital units that should be reset. It then sets all scan chains in test mode and switches the input multiplexers into reset mode; and then controls the number of shift clock cycles for shifting in the reset value to the flip-flops in the scan chain, respectively.

A system comprises a plurality of regions, wherein ones of the plurality of regions are partitioned from others of the plurality of regions and at least one of the plurality of regions is a region under test. The system comprises at least one noise generator configured to generate noise in at least the region under test, and at least one noise monitor configured to monitor one or more effects of the noise generated in the region under test. The system comprises a test controller configured to: cause the at least one noise generator to generate the noise in at least the region under test; receive information from the at least one noise monitor indicative of the one or more effects of the noise generated in the region under test; and determine one or more conditions based on at least a portion of the received information.

A semiconductor integrated circuit (IC) comprising a time-to-digital converter (TDC) configured to measure an input-to-output delay of an I/O buffer of a pad the IC, the measured delay reflecting a connection impedance of the pad. A circuit in the IC, or a computer in communication with the IC, determines electrical connection integrity of the pad based on the measured delay of the I/O buffer.

The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.

During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

An integrated circuit die includes a core fabric configurable to include an aging measurement circuit and a device manager coupled to the core fabric to operate the aging measurement circuit for a select period of time. The aging measurement circuit includes a counter to count transitions of a signal propagating through the aging measurement circuit during the select period of time when the aging measurement circuit is operating. The transitions of the signal counted by the counter during the select period of time are a measure of an aging characteristic of the integrated circuit die.

An exemplary system includes a photodetector configured to generate a plurality of photodetector output pulses over time as a plurality of light pulses are applied to and scattered by a target, a TPSF generation circuit configured to generate, based on the photodetector output pulses, a TPSF representative of a light pulse response of the target, and a control circuit configured to direct the TPSF generation circuit to selectively operate in different resolution modes.

Testing clock division circuitry includes generating pseudo random test pattern bits for scan chain logic in programmable clock division logic circuitry and divided clock counter circuitry. A shift clock is used to shift the test pattern bits into the scan chain logic. A capture clock signal is used in the programmable clock division logic during a non-test mode of operation. The shift clock is used to provide output shift bits from the scan chain logic to a multi-input shift register (MISR). Once all the output shift bits for the test pattern bits are provided to the MISR, a final test signature from the MISR is compared to an expected test signature to determine whether the programmable clock division logic circuitry and divided clock counter circuitry are free of faults.

A method includes mapping an aging measurement circuit (AMC) into the core fabric of an FPGA and operating the AMC for a select time period. During the select period of time, the AMC counts transition of a signal propagating through the AMC. Timing information based on the counted transitions is stored in a timing model in a memory. The timing information represents an aging characteristic of the core fabric at a time that the AMC is operated. An EDA toolchain uses the timing information in the timing model to generate a timing guard-band for the configurable IC die. The AMC is removed from the core fabric and another circuit device is mapped and fitted into the core fabric using the generated timing guard-band models. The circuit device is operated in the configurable IC die based on the timing guard-band models.

The present disclosure describes a method for analyzing signal waveforms produced by integrated circuits. The method includes determining characteristic points of a control signal, and each characteristic point includes a corresponding time value and represents an edge change of the control signal. The method also includes determining sets of data sampling points. Each set of data sampling points is located between adjacent characteristic points of the characteristic points. The method further includes obtaining data values of a signal waveform, and a data value of the signal waveform is obtained at a data sampling point of the sets of data sampling points. The method further includes obtaining data values of a reference waveform, and a data value of the reference waveform is obtained at the data sampling point and determining a difference between the data value of the signal waveform and the data value of the reference waveform.