A method for determining the propagation delay of each path in an integrated circuit is provided herein. The method includes determining, in a worst-based mode, whether a propagation delay of a selected path exceeds a timing requirement; determining, in a path-based mode, whether the propagation delay of a selected path exceeds the timing requirement; and when the selected path exceeds the timing requirement in the path-based mode, lowering the cell delay of each cell in the selected path.

Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.

During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Systems, methods, and computer readable medium described herein relate to techniques for characterizing and/or anomaly detection in integrated circuits such as, but not limited to, field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). In one example aspect of certain example embodiments, a fully digital technique relies on the pulse width of signals propagated through a path under test. In another example aspect, the re-configurability of the integrated circuit is leveraged to combine the pulse propagation technique with a delay characterization technique to yield better detection of certain type of Trojans and the like. Another example aspect provides for running the test through reconfigurable path segments in order to isolate and identify anomalous circuit elements. Yet another example aspect provides for performing the characterization and anomaly detection without requiring golden references and the like.

This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

A monitor circuit (301) for monitoring changes in an input digital value of a register circuit comprises a data input (302) configured to receive a copy of the input digital value of said register circuit, and one or more triggering signal inputs (303) configured to receive one or more triggering signals. One or more triggering edges thereof define an allowable time limit before which a digital value must appear at a data input of said register circuit to become properly stored in said register circuit. The monitor circuit comprises a data event (DE) output (305), so that said monitor circuit is configured to produce a DE signal at said DE output (305) in response to a digital value at said data input (302) changing within a time window defined by said one or more triggering signals.

A deskew fixture includes first and second deskew probe points for contacting first and second probes, respectively, during deskew calibration, a signal generating circuit for generating a calibration signal provided to the first and second deskew probe points, and a feedback loop for automatically self-calibrating the deskew fixture. The feedback loop includes first and second analog to digital converters (ADCs) for digitizing the calibration signal at the first and second deskew probe points while contacting the first and second probes, respectively, to provide first and second digitized calibration signals, and a processing unit programmed to determine inherent skew of the deskew fixture between the first and second skew probe points using the first and second digitized calibration signals, and to provide the determined inherent skew to a test instrument for use in the deskew calibration of the first and second probes.

An unbalanced multiplexer and a scan flip-flop including the unbalanced multiplexer, wherein the unbalanced multiplexer includes a first transmission circuit transmitting a first input signal to an output terminal according to a logic state of a selection signal; and a second transmission circuit transmitting a second input signal to the output terminal according to the logic state of the selection signal. A delay characteristic of a first transmission path from a first input terminal to the output terminal along which the first input signal of the first transmission circuit is transmitted, and a delay characteristic of a second transmission path from a second input terminal to the output terminal along which the second input signal of the second transmission circuit is transmitted, are set differently.

A method to control aging of a system on chip comprising one or more devices including semiconductor circuit components and at least one aging controller monitoring electrical signals circulating inside the system on chip. The method comprises steps of stressing at least one device of the system on chip by varying hardware parameters related to its operating mode, comparing at least one parameter associated with an electrical signal produced by the at least one device with a reference parameter to determine a difference corresponding to an operating age value of the at least one device, if the operating age value equals or exceeds a threshold age value, determining a stress state value and modifying the operating mode of the at least one device according to the stress state value. A system on chip performing the method is also disclosed.