Embodiments are directed to a computer implemented method and system for the testing, characterization and diagnostics of integrated circuits. A system might include a device under test, such as an integrated circuit, that includes an adaptive microcontroller. The method includes loading a testing program for execution by the adaptive microcontroller, causing the microcontroller to execute the testing program. Once results from the testing program are received, the testing program can be adaptively modified based on the results. The modified testing program can be run again. The testing program can modify parameters of the integrated circuit that are not externally accessible. Other embodiments are also disclosed.

Embodiments are directed to a system for synchronizing switching events. The system includes a controller, a clock generator communicatively coupled to the controller and a delay chain communicatively coupled to the controller. The delay chain is configured to perform a plurality of delay chain switching events in response to an input to the delay chain. The controller is configured to initiate a synchronization phase that includes enabling the clock generator to provide as an input to the delay chain a clock generator output at a synchronization frequency, wherein the clock generator output passing through the delay chain synchronizes the plurality of delay chain switching events to occur at the synchronization frequency resulting in a frequency of an output of the delay chain being synchronized to the synchronization frequency of the clock generator output.

An example integrated circuit (IC) die in a multi-die IC package, the multi-die IC package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS), is described. The IC die includes a Joint Test Action Group (JTAG) controller having a JTAG interface that includes a TDI, a TDO, a TCK, and a TMS, a first output coupled to first routing in the multi-die IC package, a first input coupled to the first routing or to second routing in the multi-die IC package, a master return path coupled to the first input, and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller, and selectively couple, in response to a first control signal, the TDO of the TAP to either the master return path or the TDO.

The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer’s system. Additional embodiments are also provided and described in the disclosure.

An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

An integrated circuit for on-chip speed grading comprises test circuitry comprising scan chains and a test controller; and wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry. The wide-range clock signal generation circuitry is configured to generate a wide-range test clock signal for the test circuitry to conduct a structural delay test for on-chip speed grading. The wide-range test clock signal is generated based on a test clock signal associated with the test circuitry, a frequency range selection signal and a frequency setting signal.

Embodiments of the present disclosure may include a system for scanning a circuit, the embodiments including flip-flops, latches interleaved between the flip-flops, multiplexers configured to propagate scan data between the flip-flops and latches, and scan logic configured to control the multiplexers to load test data into the flip-flops and latches. A first pair of latches are interleaved between a first pair of flip-flops.

A shift register circuit generates a clock enable signal in response to a start signal and in response to a clock signal. The shift register circuit generates multiple pulses in the clock enable signal in response to a single transition in the start signal and in response to control signals having values that indicate to generate more than one pulse in the clock enable signal. A multiplexer circuit provides an output signal for testing an electronic circuit based on an input signal or based on the clock signal in response to the clock enable signal.

Disclosed is a device for detecting the margin of a circuit operating at an operating speed. The device includes: a signal generating circuit generating an input signal including predetermined data; a first adjustable delay circuit delaying the input signal by a first delay amount and thereby generating a delayed input signal; a circuit under test performing a predetermined operation based on a predetermined operation timing and thereby generating a to-be-tested signal according to the delayed input signal; a second adjustable delay circuit delaying the to-be-tested signal by a second delay amount and thereby generating a delayed to-be-tested signal; a comparison circuit comparing the data included in the delayed to-be-tested signal with the predetermined data based on the predetermined operation timing and thereby generating a comparison result; and a calibration circuit determining whether the circuit under test passes a speed test according to the comparison result.

A detection circuit is configured to detect phase information between two clock signals of different frequencies, and the two clock signals include a low frequency clock signal and a high frequency clock signal. The detection circuit includes: a signal generation module, configured to detect the low frequency clock signal at an edge of the high frequency clock signal to generate a to-be-sampled signal, and generate a target sampling signal when the high frequency clock signal is kept at a preset level and the low frequency clock signal meets a preset condition; and a sampling module, connected with the signal generation module and configured to detect the to-be-sampled signal at an edge of the target sampling signal to generate a detection result signal.