An optical-electrical device can implement a feedback-based control loop for temperature of the device during component calibration. The optical-electrical device can implement compressed air to vary the device temperature during calibration. Additionally, non-active components of the device can be provided current to vary the temperature of the device in concert with the provided compressed air. Additional calibration temperatures can be implemented by activating and deactivating additional non-active components in the device, such as light sources, optical amplifiers, and modulators.

A hybrid optical-electrical automated testing equipment (ATE) system can implement an optical test assembly that includes an electrical interface and an optical interface with an optical-electrical device under test. The optical assembly can include a socket on which the device is placed by the ATE system to connect electrical and optical connections. The optical connections can couple light through the socket and the optical assembly to one or more testing devices to perform efficient testing of optical devices, such as high-speed optical transceivers.

A hybrid automated testing equipment (ATE) system can simultaneously test electrical and optical components of a device under test, such as an optical transceiver. The device under test can be a multilane optical transceiver that transmits different channels of data on different lanes. The hybrid ATE system can include one or more light sources and optical switches in an optical test lane selector to selectively test and calibrate each optical and electrical components of each lane of the device under test.

A hybrid optical-electrical automated testing equipment (ATE) system can implement a workpress assembly that can interface with a device under test (DUT) and a load board that holds the DUT during testing, analysis, and calibration. A test hand can actuate to position the DUT on a socket and align one or more alignment features. The workpress assembly can include two optical interfaces that are optically coupled such that light can be provided to a side of the DUT that is facing away from the load board, thereby enabling the ATE system to perform simultaneous optical and electrical testing of the DUT.

A chip detection method includes: providing a chip to be tested, the chip having multiple one-time programmable memories (OTPMs); transmitting a test signal to the chip to maintain the OTPMs in the chip in a latched state; and detecting whether the chip emits a low-light signal, and if yes, determining that an OTPM is leaky. The chip detection method and device can detect an OTPM that is burnt through by mistake, and can also detect an OTPM that has slight leakage, thereby preventing a defective product with a potential burn-through risk from entering a subsequent production process.

An optical-electrical device can implement a feedback-based control loop for temperature of the device during component calibration. The optical-electrical device can implement compressed air to vary the device temperature during calibration. Additionally, non-active components of the device can be provided current to vary the temperature of the device in concert with the provided compressed air. Additional calibration temperatures can be implemented by activating and deactivating additional non-active components in the device, such as light sources, optical amplifiers, and modulators.

An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

A method of testing a photonics die at the wafer level includes providing a sacrificial waveguide and a grating coupler at least partially in a scribe line between dies of a wafer, performing one or more tests on the dies of the wafer via the sacrificial waveguide and grating coupler in the scribe line, and removing the sacrificial waveguide during separation of the dies of the wafer.

Methods and apparatuses for testing a photonic integrated circuit and a corresponding sample holder and a photonic integrated circuit are provided. Here, a location for an illumination light beam can be selected by way of a scanning device, with the result that targeted coupling of the illumination light into the photonic integrated circuit is made possible.

In one embodiment, an apparatus includes a bi-directional coupler for coupling an upstream signal and a downstream signal to a termination load. A test point detection mechanism is configured to detect when a test point device is inserted in a test point connector. The test point device is configured to perform a test of the upstream signal or the downstream signal. A switch is configured to switch from being coupled to the termination load to being coupled to the test point device when the test point device is detected as being inserted in the test point connector. The switch is configured to switch from being coupled to being coupled to the test point device to the termination load when the test point device is detected as being removed from being inserted in the test point connector.