The present disclosure provides memory devices and methods for using shared latch elements thereof. A memory device includes a substrate, an interposer disposed over the substrate, and a logic die and stacked memory dies disposed over the interposer. In the logic die, the test generation module performs a memory test operation for the memory device. The functional elements stores functional data in latch elements during a functional mode of the memory device. The repair analysis module determines memory test/repair data based on the memory test operation. The memory test/repair data comprises memory addresses of faulty memory storage locations of the memory device that are identified during the memory test operation. The repair analysis module configures the latch elements into a scan chain, accesses the memory test/repair data during the test mode of the memory device, and repairs the memory device using the memory test/repair data.

A safety mechanism device includes measuring whether a first output signal or results meets dynamically adjustable boundary criterion. The safety mechanism compares the first output signal with at least one boundary signal that is dynamically adjusted. The safety mechanism can produce a dynamically or automatically adjusted boundary signal using a second output signal. The second output signal can mimic the first output signal.

A safety mechanism device includes measuring whether a first output signal or results meets dynamically adjustable boundary criterion. The safety mechanism compares the first output signal with at least one boundary signal that is dynamically adjusted. The safety mechanism can produce a dynamically or automatically adjusted boundary signal using a second output signal. The second output signal can mimic the first output signal.

A tool for performing a logic built-in self-test of an electronic circuit operating on a clock cycle basis. The tool stores a configurable test signature in a random-access memory together with a pattern counter for a test pattern, wherein a number of the at least one additional signature register corresponds to a number of entries in the random access memory. The tool determines an error based, at least in part, on a compare operation for a given test pattern, wherein the compare operation determines whether the test signature in the first signature register before a capture cycle of a next test pattern differs from the corresponding configurable test signature. The tool stores the error in a corresponding additional signature register.

A tool for performing a logic built-in self-test of an electronic circuit operating on a clock cycle basis. The tool stores a configurable test signature in a random-access memory together with a pattern counter for a test pattern, wherein a number of the at least one additional signature register corresponds to a number of entries in the random access memory. The tool determines an error based, at least in part, on a compare operation for a given test pattern, wherein the compare operation determines whether the test signature in the first signature register before a capture cycle of a next test pattern differs from the corresponding configurable test signature. The tool stores the error in a corresponding additional signature register.

A non-transitory computer-readable storage medium stores instructions, which when executed by a processing device of a diagnostic server, cause the processing device to perform certain operations. The operations include receiving, from a processing chamber, (i) measurement values of a combined signal that is based on an injection of an alternating signal wave onto a first output signal of a controller of the processing chamber, and (ii) measurement values of a second output signal of the controller that incorporates feedback from the processing chamber. The operations further include generating, based on the measurement values of the combined signal and the measurement values of the second output signal of the controller, a baseline bode fingerprint pertaining to a state associated with the processing chamber. The operations further include storing, in computer storage, the baseline bode fingerprint to be used in performing diagnostics of the processing chamber.

A non-transitory computer-readable storage medium stores instructions, which when executed by a processing device of a diagnostic server, cause the processing device to perform certain operations. The operations include receiving, from a processing chamber, (i) measurement values of a combined signal that is based on an injection of an alternating signal wave onto a first output signal of a controller of the processing chamber, and (ii) measurement values of a second output signal of the controller that incorporates feedback from the processing chamber. The operations further include generating, based on the measurement values of the combined signal and the measurement values of the second output signal of the controller, a baseline bode fingerprint pertaining to a state associated with the processing chamber. The operations further include storing, in computer storage, the baseline bode fingerprint to be used in performing diagnostics of the processing chamber.

During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.