Methods for detecting a glitch at a high sampling rate are provided. In some embodiments, a method includes the following steps: S1, acquiring to-be-identified data; S2, processing the to-be-identified data to obtain normal sampling data; and S3, performing glitch identification on the to-be-identified data to obtain a glitch position of the normal sampling data. In other embodiments, the disclosure provides a system for detecting a glitch at a high sampling rate and for implementing the method for detecting a glitch at a high sampling rate. The system includes an acquisition unit and a glitch identification unit. The acquisition unit acquires and processes the to-be-identified data to obtain the normal sampling data, and the glitch identification unit performs glitch identification on the to-be-identified data to obtain the glitch position of the normal sampling data.

Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Testing of at least one source by a destination is provided, which comprises: (i) the destination supplies a test signal towards the at least one source; (ii) at the at least one source, determining a second output signal based on a first output signal and the test signal via a first function; (iii) conveying the second output signal to the destination; (iv) at the destination, determining a received signal based on the second output signal received from the at least one source and based on the test signal via a second function; and (v) determining whether an error occurred based on the received signal. Also, an according system is provided.

Testing of at least one source by a destination is provided, which comprises: (i) the destination supplies a test signal towards the at least one source; (ii) at the at least one source, determining a second output signal based on a first output signal and the test signal via a first function; (iii) conveying the second output signal to the destination; (iv) at the destination, determining a received signal based on the second output signal received from the at least one source and based on the test signal via a second function; and (v) determining whether an error occurred based on the received signal. Also, an according system is provided.

A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

A system includes a first integrated circuit including a first interface circuit with a first transmit pin and a first receive pin, and a first test circuit. The system also includes a second integrated circuit including a second interface circuit with a second receive pin coupled to the first transmit pin, and a second transmit pin coupled to the first receive pin. The second integrated circuit further includes a second test circuit configured to route signals from the second receive pin to the second transmit pin, such that the sent test signal is received by the second receive pin, bypasses the second test circuit, and is routed to the second transmit pin. The first test circuit is further configured to receive the routed test signal on the first receive pin via the second conductive path.

Aspects of the invention include a phase rotator, that is located at a built-in self-test (BIST) path of a receiver, receiving a clock signal from an on-chip clock. The phase rotator shifts the phases of the clock signal. The phase rotator transmits the shifted clock signal to a binary sequence generator, that is located at the receiver. The binary sequence generator outputs a binary sequence, where the binary sequence generator is driven by the shifted clock signal.