The signal toggling detection and correction circuit includes a flip-flop, a checker circuit, and a fault monitoring circuit that includes a restoration circuit. Based on faults such as soft errors and unintended bit toggles in the flip-flop, a flop output signal toggles. A set of checker signals outputted by the checker circuit may toggle based on toggling of the flop output signal and a restoration signal of the restoration circuit. Based on the toggling of at least one checker signal, the fault monitoring circuit determines whether the flip-flop or the checker circuit is faulty. When the checker circuit is faulty, the fault monitoring circuit corrects the toggling of at least one checker signal. When the flip-flop is faulty, the fault monitoring circuit corrects the toggling of one of the toggled flop output signal or the restoration signal and further corrects the toggled checker signal.

The signal toggling detection and correction circuit includes a flip-flop, a checker circuit, and a fault monitoring circuit that includes a restoration circuit. Based on faults such as soft errors and unintended bit toggles in the flip-flop, a flop output signal toggles. A set of checker signals outputted by the checker circuit may toggle based on toggling of the flop output signal and a restoration signal of the restoration circuit. Based on the toggling of at least one checker signal, the fault monitoring circuit determines whether the flip-flop or the checker circuit is faulty. When the checker circuit is faulty, the fault monitoring circuit corrects the toggling of at least one checker signal. When the flip-flop is faulty, the fault monitoring circuit corrects the toggling of one of the toggled flop output signal or the restoration signal and further corrects the toggled checker signal.

A random noise generator for generating a plurality of random noise samples per clock cycle, the noise samples having a distribution. The random noise generator comprises at least a first comparator unit and a second comparator unit, the first comparator unit configured to generate a first plurality of samples representing a high-probability part of the distribution and the second comparator unit configured to generate a second plurality of samples representing a low-probability part of the distribution; and a random selection unit connected to at least the first comparator unit and the second comparator unit. The random selection unit is configured to receive the first plurality of samples generated by the first comparator unit and the second plurality of samples generated by the second comparator unit, to output a random selection of samples from the first plurality of samples and the second plurality of samples.

A random noise generator for generating a plurality of random noise samples per clock cycle, the noise samples having a distribution. The random noise generator comprises at least a first comparator unit and a second comparator unit, the first comparator unit configured to generate a first plurality of samples representing a high-probability part of the distribution and the second comparator unit configured to generate a second plurality of samples representing a low-probability part of the distribution; and a random selection unit connected to at least the first comparator unit and the second comparator unit. The random selection unit is configured to receive the first plurality of samples generated by the first comparator unit and the second plurality of samples generated by the second comparator unit, to output a random selection of samples from the first plurality of samples and the second plurality of samples.

An integrated circuit includes logic circuits, a logic analyzer circuit, and a multiplexer circuit configurable to provide a value of a signal selected from one of the logic circuits to the logic analyzer circuit. The logic analyzer circuit is configured to store the value of the signal selected by the multiplexer circuit. A method is provided for capturing signals within an integrated circuit. The method includes providing a first logic signal from a first logic circuit to a multiplexer circuit, providing a second logic signal from a second logic circuit to the multiplexer circuit, selecting one of the first logic signal or the second logic signal as a selected signal using the multiplexer circuit, and storing a value of the selected signal in the logic analyzer circuit in the integrated circuit.

An integrated circuit includes logic circuits, a logic analyzer circuit, and a multiplexer circuit configurable to provide a value of a signal selected from one of the logic circuits to the logic analyzer circuit. The logic analyzer circuit is configured to store the value of the signal selected by the multiplexer circuit. A method is provided for capturing signals within an integrated circuit. The method includes providing a first logic signal from a first logic circuit to a multiplexer circuit, providing a second logic signal from a second logic circuit to the multiplexer circuit, selecting one of the first logic signal or the second logic signal as a selected signal using the multiplexer circuit, and storing a value of the selected signal in the logic analyzer circuit in the integrated circuit.

The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

A non-transitory computer-readable storage medium stores instructions, which when executed by a processing device of a diagnostic server, cause the processing device to perform certain operations. The operations include receiving, from a processing chamber, (i) measurement values of a combined signal that is based on an injection of an alternating signal wave onto a first output signal of a controller of the processing chamber, and (ii) measurement values of a second output signal of the controller that incorporates feedback from the processing chamber. The operations further include generating, based on the measurement values of the combined signal and the measurement values of the second output signal of the controller, a baseline bode fingerprint pertaining to a state associated with the processing chamber. The operations further include storing, in computer storage, the baseline bode fingerprint to be used in performing diagnostics of the processing chamber.

A non-transitory computer-readable storage medium stores instructions, which when executed by a processing device of a diagnostic server, cause the processing device to perform certain operations. The operations include receiving, from a processing chamber, (i) measurement values of a combined signal that is based on an injection of an alternating signal wave onto a first output signal of a controller of the processing chamber, and (ii) measurement values of a second output signal of the controller that incorporates feedback from the processing chamber. The operations further include generating, based on the measurement values of the combined signal and the measurement values of the second output signal of the controller, a baseline bode fingerprint pertaining to a state associated with the processing chamber. The operations further include storing, in computer storage, the baseline bode fingerprint to be used in performing diagnostics of the processing chamber.