A semiconductor integrated circuit includes scan chains, each of which includes a serial connection of sequential circuits and performs a shift register operation in a scan test; and an integrated clock gating (ICG) chain composed by coupling, to one another, ICG circuits, each of which individually supplies a corresponding one of the scan chains with a circuit clock signal to operate the sequential circuits. In the ICG chain, an ICG enable propagation signal for controlling timing when the ICG circuits output the circuit clock signals propagates through a signal line and is input sequentially to the ICG circuits. The ICG circuits output the circuit clock signals at respective timings that are different among the scan chains.

A semiconductor integrated circuit includes scan chains, each of which includes a serial connection of sequential circuits and performs a shift register operation in a scan test; and an integrated clock gating (ICG) chain composed by coupling, to one another, ICG circuits, each of which individually supplies a corresponding one of the scan chains with a circuit clock signal to operate the sequential circuits. In the ICG chain, an ICG enable propagation signal for controlling timing when the ICG circuits output the circuit clock signals propagates through a signal line and is input sequentially to the ICG circuits. The ICG circuits output the circuit clock signals at respective timings that are different among the scan chains.

An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode.

An apparatus of a multi-chip package (MCP) of a functional safety system, comprises a processor to be configured as a master chip in a master-slave arrangement with a slave chip in the MCP, and a memory coupled to the processor to store one or more infield test scan patterns. The processor includes a bock to couple the master chip to the slave chip via a high-speed input/output (IO) interface to retrieve the one or more infield test scan patterns from the memory via the master chip, and to provide the one or more infield test scan patterns to the slave chip via the high-speed IO interface in response to the functional safety system entering an infield test mode.

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

A flip flop includes a master latch and a slave latch. The master latch includes a delay circuit configured to receive a clock signal and generate a first internal signal, and is configured to generate an internal output signal by latching a data signal based on the first internal signal. The slave latch is configured to generate a final signal by latching the internal output signal. The delay circuit is further configured to generate the first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level and generate the first internal signal based on the data signal when the clock signal has a second logic level.

A flip flop includes a master latch and a slave latch. The master latch includes a delay circuit configured to receive a clock signal and generate a first internal signal, and is configured to generate an internal output signal by latching a data signal based on the first internal signal. The slave latch is configured to generate a final signal by latching the internal output signal. The delay circuit is further configured to generate the first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level and generate the first internal signal based on the data signal when the clock signal has a second logic level.

Aspects of the invention include a phase rotator, that is located at a built-in self-test (BIST) path of a receiver, receiving a clock signal from an on-chip clock. The phase rotator shifts the phases of the clock signal. The phase rotator transmits the shifted clock signal to a binary sequence generator, that is located at the receiver. The binary sequence generator outputs a binary sequence, where the binary sequence generator is driven by the shifted clock signal.

Aspects of the invention include a phase rotator, that is located at a built-in self-test (BIST) path of a receiver, receiving a clock signal from an on-chip clock. The phase rotator shifts the phases of the clock signal. The phase rotator transmits the shifted clock signal to a binary sequence generator, that is located at the receiver. The binary sequence generator outputs a binary sequence, where the binary sequence generator is driven by the shifted clock signal.