Disclosed are an facilitating debugging electronic device, system and method, reasonably integrates the power-supply interface and the signal interface of the electronic device, matches the conventional output end of the electronic device with the master device, realizes the debugging of electronic devices including semi-finished products of PACKAGE (SMD)/PCBA/COB modules and electronic products, partly overcomes the technical problem of the increase of product volume and cost, which caused by setting different interfaces on electronic devices for various testing, burning and correcting purposes. The present disclosure also partly realizes the debugging of electronic devices with fewer external interfaces, which contributes to the miniaturization of electronic devices such as semi-finished products of PACKAGE (SMD)/PCBA/COB modules and electronic products, and guarantees the quality of electronic products by implementing the waterproof, dustproof and pleasing design of the housing structure of devices and achieves economic and social benefits.

Disclosed are an facilitating debugging electronic device, system and method, reasonably integrates the power-supply interface and the signal interface of the electronic device, matches the conventional output end of the electronic device with the master device, realizes the debugging of electronic devices including semi-finished products of PACKAGE (SMD)/PCBA/COB modules and electronic products, partly overcomes the technical problem of the increase of product volume and cost, which caused by setting different interfaces on electronic devices for various testing, burning and correcting purposes. The present disclosure also partly realizes the debugging of electronic devices with fewer external interfaces, which contributes to the miniaturization of electronic devices such as semi-finished products of PACKAGE (SMD)/PCBA/COB modules and electronic products, and guarantees the quality of electronic products by implementing the waterproof, dustproof and pleasing design of the housing structure of devices and achieves economic and social benefits.

A non-transitory computer-readable recording medium stores an analysis program for causing a computer to execute a process including: reading circuit data; trying to generate test data for a delay fault to be targeted; analyzing whether an underkill is caused when the targeted delay fault results in a redundant fault; and presenting circuit modification locations to avoid the underkill, based on an analysis result, when the underkill is caused.

The present application provides a parameter setting method and apparatus, a system, and a storage medium. The parameter setting method includes: obtaining first setting values of multiple memory parameters and storage locations of the multiple memory parameters in a non-volatile memory; generating a first parameter setting instruction according to the first setting value and the storage location of each memory parameter; and sending the first parameter setting instruction to a test device, so that the test device sets the memory parameter stored at the storage location in the non-volatile memory as the first setting value.

A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.

A system comprises a plurality of regions, wherein ones of the plurality of regions are partitioned from others of the plurality of regions and at least one of the plurality of regions is a region under test. The system comprises at least one noise generator configured to generate noise in at least the region under test, and at least one noise monitor configured to monitor one or more effects of the noise generated in the region under test. The system comprises a test controller configured to: cause the at least one noise generator to generate the noise in at least the region under test; receive information from the at least one noise monitor indicative of the one or more effects of the noise generated in the region under test; and determine one or more conditions based on at least a portion of the received information.

One embodiment provides a method and a system for generating test vectors for testing a computational system. During operation, the system obtains a design of the computational system, the design comprising an original system. The system generates a design of a fault-augmented system block by adding a plurality of fault-emulating subsystems to the original system; generates a design of an equivalence-checking system based on the original system and the fault-augmented system block; encodes the design of the equivalence-checking system into a logic formula, with variables within the logic formula comprising inputs and outputs of the original system and inputs and outputs of the fault-augmented system block; and solves the logic formula to obtain a test vector used for testing at least one fault in the computational system.

The present disclosure describes exemplary methods and systems that are applicable for hardware authentication, counterfeit detection, and in-field tamper detection in both printed circuit board and/or integrated circuit levels by utilizing random variations in boundary-scan path delay and/or current in the industry-standard JTAG-based design-for-test structure to generate unique device identifiers.

A memory temperature controlling method and a memory temperature controlling system are provided. The method includes: performing, by a testing equipment, test modes on a memory storage device, and obtaining a first internal temperature of a memory control circuit unit, a second internal temperature of each memory package and a surface temperature of each memory package to establish a linear relationship expression of the first internal temperature, the second internal temperature and the surface temperature; using, by the memory storage device, the linear relationship expression to calculate a predicted surface temperature of a rewritable non-volatile memory based on a first current internal temperature of the memory control circuit unit and a second current internal temperature of each memory package; adjusting, by the memory storage device, an operating frequency for accessing the rewritable non-volatile memory based on the predicted surface temperature.

A memory temperature controlling method and a memory temperature controlling system are provided. The method includes: performing, by a testing equipment, test modes on a memory storage device, and obtaining a first internal temperature of a memory control circuit unit, a second internal temperature of each memory package and a surface temperature of each memory package to establish a linear relationship expression of the first internal temperature, the second internal temperature and the surface temperature; using, by the memory storage device, the linear relationship expression to calculate a predicted surface temperature of a rewritable non-volatile memory based on a first current internal temperature of the memory control circuit unit and a second current internal temperature of each memory package; adjusting, by the memory storage device, an operating frequency for accessing the rewritable non-volatile memory based on the predicted surface temperature.