A system-on-chip integrated circuit device includes a plurality of functional circuit modules, at least a first circuit module of the plurality of functional circuit modules operating under a first protocol, the first protocol being an interface protocol for communicating outside the system-on-chip integrated circuit device, an interconnect fabric coupled to the functional circuit modules in the plurality of functional circuit modules, and a built-in self-test circuit module coupled to the interconnect fabric. The built-in self-test circuit is configured to test one or more selected functional circuit modules in the plurality of functional circuit modules, including at least the first circuit module under the first protocol for communicating outside the system-on-chip integrated circuit device, by routing test data through the one or more selected functional circuit modules.

Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

A method includes identifying state holding pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design, splitting each pattern of a plurality of patterns into a first part and a second part, reformatting the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns. The length of the first part is a function of a number of the identified pipeline stages.

The present invention relates to a self diagnostic apparatus for an electronic device, which includes a vector memory configured to store a test function code for testing a device under test (DUT) equipped with a plurality of cores which perform arithmetic operations, a function test expected value corresponding to a function test according to the test function code, a design for test (DFT) test code, a DFT test expected value corresponding to a DFT test according to the DFT test code, and a non-test function code for a general arithmetic operation or an operation of the DUT; a test data storage configured to store test data including a DFT test code result value which is a result of the DFT test according to the DFT test code, a test function code result value which is a result of the function test according to the test function code, and a non-test function code result value which is a result of the function test according to the non-test function code; and a safety region test controller configured to select one among the test function code, the DFT test code, and the non-test function code to select a test mode, control an environmental variable of a test signal applied to the DUT in response to the selected test mode and test the DUT, compare the function test expected value stored in the vector memory with the test function code result value stored in the test data storage, and compare the DFT test expected value stored in the vector memory with the DFT test code result value stored in the test data storage to output comparison result information.

A circuit comprises: scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses; a decompressor configured to decompress compressed test patterns into the test patterns; a test response compactor configured to compact the test responses; and shuffler circuitry inserted between outputs of the scan chains and inputs of the test response compactor, the shuffler circuitry comprising state elements configured to delay output signals from some of the scan chains for one or more clock cycles based on a control signal, the control signal varying with the test patterns.

Systems, methods, and computer program products directed to testing a System-in-a-Package (SIP) using an Automatic Test Equipment (ATE) machine. A functional representation of one or more tests to be performed in the SIP is loaded in a memory located on a load board, the load board located on the ATE machine. A test controller located on at least one of the SIP and the load board is caused to retrieve and store the one or more tests to be performed in the SIP. The test controller is instructed to conduct the one or more tests in the SIP.

An augmented simulation model can be created of an integrated circuit (IC) design by inserting a switch in a simulation model of the IC design between an output of a scan cell and an input of a combinational logic cloud. A simulation enable signal can be used to control the switch. Next, an IC design simulation environment can be generated based on the augmented simulation model. The IC design can be verified by using the IC design simulation environment. The simulation enable signal can be activated when the combinational logic cloud is desired to be simulated by the IC design simulation environment.

A crosstalk pattern detecting device and a detecting method are provided by the application. The conventional combined module is implemented as an microcontroller unit in the application and parameters of crosstalk pattern detecting modes are updated during non-display period of a display panel so that a number of the detected patterns can be increased without changing the hardware, and as a result, hardware resources can be saved.

A crosstalk pattern detecting device and a detecting method are provided by the application. The conventional combined module is implemented as an microcontroller unit in the application and parameters of crosstalk pattern detecting modes are updated during non-display period of a display panel so that a number of the detected patterns can be increased without changing the hardware, and as a result, hardware resources can be saved.

An apparatus includes a daughter die (DD) logic, and an arbitrator connected to the DD logic, and connected to an external testing device and a main die (MD) included in a multi-chip package (MCP). The apparatus further includes an enable logic configured to receive a message from the MD, based on the received message, determine whether the MD or the external testing device is enabled to access the DD logic, and based on the external testing device being determined to be enabled to access the DD logic, control the arbitrator to enable the external testing device to access the DD logic.