A deterioration estimation apparatus includes a storage processing unit and a calculation unit. The storage processing unit acquires a plurality of models from a model generation apparatus, and stores the models in a model storage unit. A plurality of models are generated by performing machine-learning on training data, the training data using, as input values, measurement data for training indicating a result of measuring a state of a storage battery when the number of charge and discharge times is α.sub.i to α.sub.j (where j≥i), and using, as a target value, SOH indicating a deterioration state of the storage battery when the number of charge and discharge times is β (where β>α.sub.j). The calculation unit uses a plurality of models stored in a model storage unit to calculate an estimation result of transition of SOH of a storage battery managed by the deterioration estimation apparatus.

In accordance with an embodiment, a method includes receiving, by at least one of a plurality of battery monitoring circuits a frequency synchronization signal and measurement frequency information from a host controller, wherein the at least one of the plurality of battery monitoring circuits is connected to at least one of a plurality of battery blocks; generating, by the at least one of the plurality of battery monitoring circuits, a periodic signal based on a clock signal having a clock frequency, the measurement frequency information, and the frequency synchronization signal; obtaining, by the at least one of the plurality of battery monitoring circuits, at least one measurement value of the at least one of the plurality of battery blocks using the periodic signal; and transmitting, by the at least one of the plurality of battery monitoring circuits, the at least one measurement value to the host controller.

According to an embodiment, a storage battery management device includes: a memory configured to store therein storage battery characteristics of a storage battery unit as a storage battery characteristics table; and one or more processors coupled to the memory. The one or more processors are configured to: acquire the storage battery characteristics based on storage battery information output from the storage battery unit; update the storage battery characteristics table based on the acquired storage battery characteristics; and estimate SOC of the storage battery unit by referring to the updated storage battery characteristics table.

According to an embodiment, a storage battery management device includes: a memory configured to store therein storage battery characteristics of a storage battery unit as a storage battery characteristics table; and one or more processors coupled to the memory. The one or more processors are configured to: acquire the storage battery characteristics based on storage battery information output from the storage battery unit; update the storage battery characteristics table based on the acquired storage battery characteristics; and estimate SOC of the storage battery unit by referring to the updated storage battery characteristics table.

A Battery Management System (BMS) semiconductor device having a leakage current detection function, may include: a comparator configured to compare a voltage of a balancing terminal connected to a positive voltage terminal of a battery cell and a voltage of a lower sensing terminal connected to a negative voltage terminal of the battery cell and output a result of the comparing; an ADC connected to the upper sensing terminal and the lower sensing terminal and configured to sense a voltage difference between the upper sensing terminal connected to the positive voltage terminal of the battery cell and the lower sensing terminal; and a leakage current determining unit connected to the ADC and the comparator and configured to set a variable threshold value according to the difference value sensed by the ADC and determine whether a leakage current is generated by using the result of the comparing in the comparator and the variable threshold value.

A Battery Management System (BMS) semiconductor device having a leakage current detection function, may include: a comparator configured to compare a voltage of a balancing terminal connected to a positive voltage terminal of a battery cell and a voltage of a lower sensing terminal connected to a negative voltage terminal of the battery cell and output a result of the comparing; an ADC connected to the upper sensing terminal and the lower sensing terminal and configured to sense a voltage difference between the upper sensing terminal connected to the positive voltage terminal of the battery cell and the lower sensing terminal; and a leakage current determining unit connected to the ADC and the comparator and configured to set a variable threshold value according to the difference value sensed by the ADC and determine whether a leakage current is generated by using the result of the comparing in the comparator and the variable threshold value.

The present disclosure relates to a capacitor bank controller that automatically determines the size of a capacitor bank using wireless current sensors. The capacitor bank controller determines a first capacitor bank size estimate using voltage and current measurements from when the capacitor bank is open and when the capacitor bank is closed a first time. The capacitor bank controller determines a second capacitor bank size estimate by using voltage measurements and current measurements from when the capacitor bank is open and when the capacitor bank is closed a second time. The capacitor bank controller determines a filtered capacitor bank size estimate based on the first capacitor bank estimate and the second capacitor bank estimate and controls operation of the capacitor bank based on the filtered capacitor bank size estimate.

The present disclosure relates to a capacitor bank controller that automatically determines the size of a capacitor bank using wireless current sensors. The capacitor bank controller determines a first capacitor bank size estimate using voltage and current measurements from when the capacitor bank is open and when the capacitor bank is closed a first time. The capacitor bank controller determines a second capacitor bank size estimate by using voltage measurements and current measurements from when the capacitor bank is open and when the capacitor bank is closed a second time. The capacitor bank controller determines a filtered capacitor bank size estimate based on the first capacitor bank estimate and the second capacitor bank estimate and controls operation of the capacitor bank based on the filtered capacitor bank size estimate.

A battery monitoring device according to an embodiment monitors a state of a secondary battery block including parallel cell blocks connected in series each of which includes battery cells connected in parallel. A calculator calculates direct-current internal resistance values of the parallel cell blocks based on a differential current between first and second current values detected by a current detector, voltages of the parallel cell blocks corresponding to the first and second current values detected by a voltage detector. A determiner performs anomaly determination for the parallel cell blocks from the direct-current internal resistance values of the parallel cell blocks and a maximum value of the direct-current internal resistance values of the parallel cell blocks.

A battery monitoring device according to an embodiment monitors a state of a secondary battery block including parallel cell blocks connected in series each of which includes battery cells connected in parallel. A calculator calculates direct-current internal resistance values of the parallel cell blocks based on a differential current between first and second current values detected by a current detector, voltages of the parallel cell blocks corresponding to the first and second current values detected by a voltage detector. A determiner performs anomaly determination for the parallel cell blocks from the direct-current internal resistance values of the parallel cell blocks and a maximum value of the direct-current internal resistance values of the parallel cell blocks.