G01R31/70

Test system for checking electronic connections

Disclosed is a test system for testing electric connections, in particular soldered connections, between electronic components and a printed circuit board to be tested, characterized in that the test system includes a subassembly, which is movably mounted in a housing of the test system, and a current and/or voltage source for energizing the circuit board to be tested, the current and/or voltage source being arranged in the housing of the test system in such a way as to be movable in at least two directions in space.

Test system for checking electronic connections

Disclosed is a test system for testing electric connections, in particular soldered connections, between electronic components and a printed circuit board to be tested, characterized in that the test system includes a subassembly, which is movably mounted in a housing of the test system, and a current and/or voltage source for energizing the circuit board to be tested, the current and/or voltage source being arranged in the housing of the test system in such a way as to be movable in at least two directions in space.

Printed circuit board, method for determining engagement state between printed circuit board and flexible printed circuit and display device

A printed circuit board, a method for determining an engagement state between the printed circuit board and a flexible printed circuit, and a display device are provided. The printed circuit board includes a substrate, a connector fixed on the substrate, and configured to be connected with the flexible printed circuit, and a determining circuit connected with the connector. The secondary pin is added to the connector, and can determine together with the determining circuit, added to the substrate, connected with the secondary pin, an engagement state between the first pins of the connector, and the second pins of the flexible printed circuit.

Printed circuit board, method for determining engagement state between printed circuit board and flexible printed circuit and display device

A printed circuit board, a method for determining an engagement state between the printed circuit board and a flexible printed circuit, and a display device are provided. The printed circuit board includes a substrate, a connector fixed on the substrate, and configured to be connected with the flexible printed circuit, and a determining circuit connected with the connector. The secondary pin is added to the connector, and can determine together with the determining circuit, added to the substrate, connected with the secondary pin, an engagement state between the first pins of the connector, and the second pins of the flexible printed circuit.

AUXILIARY METHOD AND DEVICE FOR OTP ADJUSTMENT OF DISPLAY PANEL
20200411805 · 2020-12-31 ·

The application discloses an auxiliary method and device for one time programmable (OTP) adjustment of a display panel. The auxiliary method includes: crimping and conducting a flexible circuit board to a display panel bonded with a chip by means of pre-bonding, to lead a crimping impedance by the flexible circuit board; detecting the crimping impedance led by the flexible circuit board; and screening a detected crimping impedance value to determine whether the OTP adjustment is enabled, wherein when the crimping impedance value meets a preset condition, the OTP adjustment is enabled, and when the crimping impedance value does not meet the preset condition, the OTP adjustment is disabled.

METHOD FOR ESTIMATING DEGRADATION

Method for estimating degradation of a wire-bonded power semiconductor module (1) comprising: a) obtaining an indicator of degradation (Degr.sub.est_t-1); b) estimating (11) an estimated indicator of degradation (Degr.sub.est_t) by a temporal degradation model; c) obtaining (3) a set of on-line measure (X.sub.on_meas_t); then, d1) converting (13) the on-line measure (X.sub.on_meas_t) into a deducted indicator of degradation (Degr.sub.meas_t) by an electrical equivalence model, and e1) computing (15) a deviation between estimated and deducted indicator of degradation (Degr.sub.est_t; Degr.sub.meas_t); and/or d2) converting (13) the estimated indicator of degradation (Degr.sub.est_1) into a set of on-line estimation (X.sub.on_est_t), and e2) computing (15) a deviation between set of on-line measure and estimation (X.sub.on_ meas_t; X.sub.on_est_t); and f) correcting (17) the estimated indicator of degradation (Degr.sub.est_t) into a corrected estimated indicator of degradation (Degr.sub.corr_t) in function of the computed deviation.

METHOD FOR ESTIMATING DEGRADATION

Method for estimating degradation of a wire-bonded power semiconductor module (1) comprising: a) obtaining an indicator of degradation (Degr.sub.est_t-1); b) estimating (11) an estimated indicator of degradation (Degr.sub.est_t) by a temporal degradation model; c) obtaining (3) a set of on-line measure (X.sub.on_meas_t); then, d1) converting (13) the on-line measure (X.sub.on_meas_t) into a deducted indicator of degradation (Degr.sub.meas_t) by an electrical equivalence model, and e1) computing (15) a deviation between estimated and deducted indicator of degradation (Degr.sub.est_t; Degr.sub.meas_t); and/or d2) converting (13) the estimated indicator of degradation (Degr.sub.est_1) into a set of on-line estimation (X.sub.on_est_t), and e2) computing (15) a deviation between set of on-line measure and estimation (X.sub.on_ meas_t; X.sub.on_est_t); and f) correcting (17) the estimated indicator of degradation (Degr.sub.est_t) into a corrected estimated indicator of degradation (Degr.sub.corr_t) in function of the computed deviation.

MEMORY SYSTEM TESTER USING TEST PAD REAL TIME MONITORING

A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.

WORK MACHINE AND METHOD FOR DETERMINING POLARITY
20200396877 · 2020-12-17 · ·

A work machine includes a control device including a lead position detecting section to detect a lead position which is positions of a pair of leads based on imaged data imaged by an imaging device, a first detecting region setting section to set, based on the lead position detected by the lead position detecting section, a first detecting region outside the pair of leads including a part of a bottom section outside the pair of leads, a second detecting region outside the pair of leads, being opposed to the first detecting section across the pair of leads including a part of the bottom section, and a polarity determining section configured to determine the polarity of the pair of leads based on whether the mark portion exists in each of the first detecting region and the second detecting region.

WORK MACHINE AND METHOD FOR DETERMINING POLARITY
20200396877 · 2020-12-17 · ·

A work machine includes a control device including a lead position detecting section to detect a lead position which is positions of a pair of leads based on imaged data imaged by an imaging device, a first detecting region setting section to set, based on the lead position detected by the lead position detecting section, a first detecting region outside the pair of leads including a part of a bottom section outside the pair of leads, a second detecting region outside the pair of leads, being opposed to the first detecting section across the pair of leads including a part of the bottom section, and a polarity determining section configured to determine the polarity of the pair of leads based on whether the mark portion exists in each of the first detecting region and the second detecting region.