A general purpose sensor architecture integrating a surface enhanced Raman spectroscopy (SERS) substrate, a diffractive laser beam delivery substrate and a diffractive infrared detection substrate is provided that can be used to implement a low-cost, compact lab-on-a-chip biosensor that can meet the needs of large-scale infectious disease testing. The sensor architecture can also be used in any other application in which molecules present in the liquid, gaseous or solid phases need to be characterized reliably, cost-effectively and with minimal intervention by highly skilled personnel.

A device, such as an electroabsorption modulator, can modulate a light intensity by controllably absorbing a selectable fraction of the light. The device can include a substrate. A waveguide positioned on the substrate can guide light. An active region positioned on the waveguide can receive guided light from the waveguide, absorb a fraction of the received light, and return a complementary fraction of the received light to the waveguide. Such absorption produces heat, mostly at an input portion of the active region. The input portion of the active region can be thermally coupled to the substrate, which can dissipate heat from the input portion, and can help avoid thermal runaway of the device. The active region can be thermally isolated from the substrate away from the input portion, which can maintain a relatively low thermal mass for the active region, and can increase efficiency when heating the active region.

A method includes forming a first photonic die, which includes forming a first silicon waveguide, and forming a first nitride waveguide. The method further includes forming a first through-via extending into a first plurality of dielectric layers in the first photonic die, and bonding a second photonic die to the first photonic die. The second photonic die includes a second nitride waveguide. The first silicon waveguide is optically coupled to the second nitride waveguide through the first nitride waveguide. A second through-via extends into a second plurality of dielectric layers in the second photonic die.

A photonic polarization splitter rotator (PSR) includes a substrate, a first optical waveguide disposed in the substrate on a first layer, the first optical waveguide having a curved portion between a first end of the first optical waveguide and a second end of the first optical waveguide, and a second optical waveguide disposed in the substrate on a second layer, above the first layer, the second optical waveguide having a substantially rectangular shape and longitudinally arranged between the first end of the first optical waveguide and the second end of the first optical waveguide.

A method for fabricating a photonic package device is provided. The method includes patterning a semiconductor layer of a semiconductor-on-insulator (SOI) substrate into a waveguide structure and at least one first semiconductor pillar; forming a metal-dielectric stack over the waveguide structure and the first semiconductor pillar; etching an opening in the metal-dielectric stack to expose the first semiconductor pillar; etching an insulator layer of the SOI substrate to form at least one insulator cap below the first semiconductor pillar; and etching a base semiconductor substrate of the SOI substrate to form at least one second semiconductor pillar below the insulator cap.

There is set forth herein a method including building a first photonics structure using a first wafer having a first substrate, wherein the building the first photonics structure includes integrally fabricating within a first photonics dielectric stack one or more photonics device, the one or more photonics device formed on the first substrate; building a second photonics structure using a second wafer having a second substrate, wherein the building the second photonics structure includes integrally fabricating within a second photonics dielectric stack a laser stack structure active region and one or more photonics device, the second photonics dielectric stack formed on the second substrate; and bonding the first photonics structure and the second photonics structure to define an optoelectrical system having the first photonics structure bonded the second photonics structure.

A large single-photon avalanche diode (SPAD) array is integrated with optical waveguide (WG) based devices. SPAD is a very sensitive optical detector fabricated on a semiconductor chip and WG structures are also built into the same chip. WG structures are configured to accumulate SPAD detection current. Together, they form an ultra-sensitive optical detector with high-speed response and a large aperture.

An optical waveguide substrate includes: a substrate; a clad disposed on a plane of the substrate and made of a transparent material; and a plurality of cores that are surrounded by the clad, extend in parallel with the plane of the substrate and are made of a transparent material having a refractive index different from a refractive index of the clad, the cores including at least a pair of cores with diameters different from each other. The cores are provided at positions where centers of sections of the cores are all positioned in a straight line.

Embodiments herein describe using a double wafer bonding process to form a photonic device. In one embodiment, during the bonding process, an optical element (e.g., a high precision optical element) is optically coupled to an optical device in an active surface layer. In one example, the optical element comprises a nitride layer which can be patterned to form a nitride waveguide, passive optical multiplexer or demultiplexer, or an optical coupler.

A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the integrated circuits include at least one processor, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.