Patent classifications
G03F1/78
METHOD FOR RETICLE ENHANCEMENT TECHNOLOGY OF A DESIGN PATTERN TO BE MANUFACTURED ON A SUBSTRATE
Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include determining an initial mask pattern from a desired pattern for a substrate; calculating a first substrate pattern from the initial mask pattern; determining an initial set of VSB shots that will form the initial mask pattern; calculating a simulated mask pattern from the initial set of VSB shots; calculating a second substrate pattern from the simulated mask pattern; and adjusting the initial set of VSB shots, wherein the adjusting of the initial set of VSB shots creates an adjusted set of VSB shots.
METHOD FOR RETICLE ENHANCEMENT TECHNOLOGY OF A DESIGN PATTERN TO BE MANUFACTURED ON A SUBSTRATE
Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include determining an initial mask pattern from a desired pattern for a substrate; calculating a first substrate pattern from the initial mask pattern; determining an initial set of VSB shots that will form the initial mask pattern; calculating a simulated mask pattern from the initial set of VSB shots; calculating a second substrate pattern from the simulated mask pattern; and adjusting the initial set of VSB shots, wherein the adjusting of the initial set of VSB shots creates an adjusted set of VSB shots.
METHOD OF MAKING EUV MASK WITH AN ABSORBER LAYER
Embodiments of present invention provide a method of forming an extreme ultraviolet (EUV) mask. The method includes subliming a radiation-sensitive material onto a surface of an EUV blank substrate; exposing the radiation-sensitive material to an ionizing radiation to form an EUV mask pattern; and removing a portion of the radiation-sensitive material from the surface of the EUV blank substrate where the portion of the radiation-sensitive material is unexposed to the ionizing radiation. An EUV mask made therefrom, and the related radiation-sensitive material are also provided.
CRITICAL DIMENSION UNIFORMITY
A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.
METHOD OF MANUFACTURING PHOTO MASKS
In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
METHOD OF MANUFACTURING PHOTO MASKS
In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
Photomask including fiducial mark and method of making semiconductor device using the photomask
A method of making a semiconductor device includes forming at least one fiducial mark on a photomask outside of a pattern region of the photomask, and the at least one fiducial mark includes identifying information for the photomask. The method includes defining a pattern including a plurality of sub-patterns on the photomask in the pattern region based on the identifying information. The defining of the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns, or rotating the first sub-pattern about an axis perpendicular to a top surface of the photomask relative to the second sub-pattern. The method includes transferring the pattern from the photomask to a wafer.
Enforcing mask synthesis consistency across random areas of integrated circuit chips
A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties enforced include symmetry within circuit patterns and similarity across circuit patterns. The system combines mask patterns in different regions of the circuit and resolves conflicts that occur when there are multiple masks within a region.
Compensating deposition non-uniformities in circuit elements
A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.
Method of mask data synthesis and mask making
A method for mask data synthesis and mask making includes calibrating an optical proximity correction (OPC) model by adjusting a plurality of parameters including a first parameter and a second parameter, wherein the first parameter indicates a long-range effect caused by an electron-beam lithography tool for making a mask used to manufacture a structure, and the second parameter indicates a geometric feature of a structure or a manufacturing process to make the structure, generating a device layout, calculating a first grid pattern density map of the device layout, generating a long-range correction map, at least based on the calibrated OPC model and the first grid pattern density map of the device layout, and performing an OPC to generate a corrected mask layout, at least based on the generated long-range correction map and the calibrated OPC model.