Patent classifications
G03F7/203
FABRICATION OF HIGH-ASPECT RATIO NANOSTRUCTURES BY LOCALIZED NANOSPALLING EFFECT
In this work is presented a method for fabrication of high-aspect ratio structures through spalling effect. The spalling is achieved through lithography, etching and sputtering processes, thus providing the flexibility to position the spalled structures according to the application requirements. This method has been successfully demonstrated for metal-oxides and metals. The width of the fabricated structures is dependent on the thickness of the film deposited by sputtering, where structures as small as 20 nm in width have been obtained.
Underlayer material for photoresist
A method includes providing a layered structure on a substrate, the layered structure including a bottom layer formed over the substrate, a hard mask layer formed over the bottom layer, a material layer formed over the hard mask layer, and a photoresist layer formed over the material layer, exposing the photoresist layer to a radiation source, developing the photoresist layer, where the developing removes portions of the photoresist layer and the material layer in a single step without substantially removing portions of the hard mask layer, and etching the hard mask layer using the photoresist layer as an etch mask. The material layer may include acidic moieties and/or acid-generating molecules. The material layer may also include photo-sensitive moieties and crosslinking agents.
DOUBLE EXPOSURE PROCESS
A double exposure process includes providing a reticle including two different patterns arranged alternatedly in columns. A wafer covered by a photoresist is provided. Later, a double exposure process is performed. The double exposure process includes steps of: performing a first exposure by illuminating a light through the reticle to transfer patterns onto the photoresist. Later, the reticle is moved a distance of a width of one column. Finally, a second exposure is performed by illuminating the light through the reticle to transfer the patterns onto the photoresist.
PHOTORESIST-FREE PHOTOLITHOGRAPHY, PHOTOPROCESSING TOOLS, AND METHODS WITH VUV OR DEEP-UV LAMPS
A fabrication tool has at least one flat lamp photon source, or an array of flat lamps, that serve to non-thermally ablate polymer material from a surface. No photoresist is required and the desired photoablated pattern is determined by inserting a photolithographic mask between the lamp(s) and the surface to be processed. Methods of the invention pattern organic polymer and can pattern a substrate using a pattern established in an organic polymer layer on the substrate, and can also deposit materials in the pattern by breaking bonds in deposition precursors with photons from the microplasma array. Another method converts organic polymer material to have a hydrophylic surface. A tool of the invention can have width and depth comparable to a typical paperback book and a height comparable to a coffee cup.
Composition and method for manufacturing device using same
An onium salt and a composition having high sensitivity and excellent pattern characteristics such as LWR, which is preferably used for a resist composition for a lithography process using two active energy rays of a first active energy ray such as an electron beam or an extreme ultraviolet and a second active energy ray such as UV.
Method and structures for personalizing lithography
After printing common features from a primary mask into a photoresist layer located over a substrate, a functional feature which is suitable for changing functionalities or the configurations of the common features according to a chip design is selected from a library of additional functional features in a secondary mask. The selected functional feature from the secondary mask is printed into the photoresist layer to modify the common features that already exist in the photoresist layer. The selection and printing of functional feature processes can be repeated until a final image corresponding to the chip design is obtained in the photoresist layer.
Method (and related apparatus) that reduces cycle time for forming large field integrated circuits
In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.
PATTERN FORMING METHOD AND TEMPLATE MANUFACTURING METHOD
A pattern forming method includes forming a resist film having a first region, a second region, and a third region, on a substrate, irradiating the first region with light or an energy ray in a first irradiation amount, and irradiating the second region with light or an energy ray in a second irradiation amount, the second irradiation amount being smaller than the first irradiation amount. The pattern forming method also includes dissolving the resist film of the first region by using first liquid, forming a coating film on a side surface of the resist film after the resist film of the first region is dissolved, and dissolving the third region by using second liquid that is different from the first liquid.
Photoresist and manufacturing method of photoresist patterns
A photoresist and a method of manufacturing photoresist patterns are disclosed. The photoresist includes a plurality of photosensitive units, and each photosensitive unit has magnetism.
Multi fan-out package structure and method for forming the same
A package structure and method for forming the same are provided. The package structure includes a first redistribution structure formed over a substrate, and the first redistribution structure includes a first conductive line, a second conductive line and a first overlapping conductive line between the first conductive line and the second conductive line. The first conductive line has a first width, the second conductive line which is parallel to the first conductive line has a second width, and the overlapping conductive line has a third width which is greater than the first width and the second width. The package structure includes a first package unit formed over the first redistribution structure, and the first package unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function than the first die stack.