Patent classifications
G03F7/70125
Fast freeform source and mask co-optimization method
The present disclosure relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present disclosure significantly speeds up the convergence of the optimization by allowing direct computation of gradient of the cost function. According to other aspects, the present disclosure allows for simultaneous optimization of both source and mask, thereby significantly speeding the overall convergence. According to still further aspects, the present disclosure allows for free-form optimization, without the constraints required by conventional optimization techniques.
INCLUSION OF STOCHASTIC BEHAVIOR IN SOURCE MASK OPTIMIZATION
A method of generating a mask used in fabrication of a semiconductor device includes, in part, selecting a source candidate, generating a process simulation model that includes a stochastic variance band model in response to the selected source candidate, performing a first optical proximity correction (OPC) on the data associated with the mask in response to the process simulation model, assessing one or more lithographic evaluation metrics in response to the OPC mask data, computing a cost in response to the assessed one or more lithographic evaluation metrics, and determining whether the computed cost satisfies a threshold condition. In response to the determination that the computed cost does not satisfy the threshold condition, a different source candidate may be selected.
SOURCE MASK OPTIMIZATION BY PROCESS DEFECTS PREDICTION
A method of generating a mask used in fabrication of a semiconductor device includes, in part, selecting a source candidate, generating a process simulation model that includes a defect rate in response to the selected source candidate, performing a first optical proximity correction (OPC) on the data associated with the mask in response to the process simulation model, assessing one or more lithographic evaluation metrics in response to the OPC mask data, computing a cost in response to the assessed one or more lithographic evaluation metrics, and determining whether the computed cost satisfies a threshold condition. In response to the determination that the computed cost does not satisfy the threshold condition, a different source candidate may be selected.
Rule-based deployment of assist features
Several methods of reducing one or more pattern displacement errors, contrast loss, best focus shift, tilt of a Bossung curve of a portion of a design layout used in a patterning process for imaging that portion onto a substrate using a lithographic apparatus. The methods include determining or adjusting one or more characteristics of one or more assist features using the one or more rules based on one or more parameters selected from a group consisting of: one or more characteristics of one or more design features in the portion, one or more characteristics of the patterning process, one or more characteristics of the lithographic apparatus, and/or a combination selected from the foregoing.
Optimization based on machine learning
A method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic apparatus, the method including: obtaining a first source of the lithographic apparatus; classifying the first source into a class among a plurality of possible classes, based on one or more numerical characteristics of the first source, using a machine learning model, by a computer; determining whether the class is among one or more predetermined classes; only when the class is among the one or more predetermined classes, adjusting one or more source design variables to obtain a second source.
Optimization of a lithography apparatus or patterning process based on selected aberration
A method including obtaining a selected component of optical aberration of or for a lithography apparatus, under a processing condition; computing an approximate of a cost function, based on the selected component; and producing an adjustment of the lithography apparatus or a patterning process that uses the lithography apparatus, based on the approximate of the cost function.
Illumination optical unit and optical system for EUV projection lithography
An illumination optical unit for EUV projection lithography serves for obliquely illuminating an illumination field, in which an object field of a downstream imaging catoptric optical unit and a reflective object to be imaged can be arranged. A pupil generating device of the illumination optical unit is embodied so that an illumination pupil results, which brings about a dependency of an imaging telecentricity against a structure variable of the object to be imaged. This dependency is such that a dependency of the imaging telecentricity against the structure variable of the object to be imaged on account of interaction of the oblique illumination with structures of the object to be imaged is at least partly compensated for. An optical system for EUV projection lithography also has an imaging catoptric optical unit alongside an illumination optical unit and can additionally have a wavefront manipulation device.
MASK AND METHOD FOR MANUFACTURING THE SAME, LITHOGRAPHY METHOD, DISPLAY PANEL, DISPLAY DEVICE AND EXPOSURE DEVICE
A mask is provided in embodiments of the disclosure, at least including: a first light transmission area provided with a first optical filter film; and a second light transmission area provided with a second optical filter film; the first optical filter film and the second optical filter film comprise respective materials through which light of different frequency ranges is optically filtered, respectively. A method for manufacturing a mask, a lithography method, a display panel, a display device, and an exposure device are further provided in embodiments of the disclosure.
INTEGRATED CIRCUIT WITH SCRIBE LANE PATTERNS FOR DEFECT REDUCTION
In examples, a method of manufacturing an integrated circuit comprises locating a photomask between a light source and a semiconductor wafer having a photoresist layer in a wafer scribe lane of the wafer, wherein the photomask comprises: a first mask scribe lane pattern; a second mask scribe lane pattern matching the first mask scribe lane pattern; and at least one circuit pattern of the integrated circuit located between the first and second mask scribe lane patterns. The method further includes illuminating the photomask to produce in the photoresist layer of the wafer scribe lane a first exposed portion corresponding to the second mask scribe lane pattern; locating the first mask scribe lane pattern between the light source and the first exposed portion; and illuminating the photomask, wherein the first mask scribe lane pattern substantially shields non-exposed portions of the photoresist layer of the wafer scribe lane from light exposure.
Optimization of assist features and source
Disclosed herein are several methods of reducing one or more pattern displacement errors, contrast loss, best focus shift , tilt of a Bossung curve of a portion of a design layout used in a lithographic process for imaging that portion onto a substrate using a lithographic apparatus. The methods include adjusting an illumination source of the lithographic apparatus, placing assist features onto or adjusting positions and/or shapes existing assist features in the portion. Adjusting the illumination source and/or the assist features may be by an optimization algorithm.