In pattern formation method, a photomask is loaded into a lithography apparatus, an exposure light is applied to a photo resist layer formed over a substrate through or via the photomask, and the photo resist layer is developed. The photomask includes a plurality of octagonal shape patterns periodically arranged in a first direction and a second direction crossing the first direction. A width Lx of horizontal sides extending in the first direction of each of the plurality octagonal shape patterns is different from a width Ly of vertical sides extending in the second direction of each of the plurality octagonal shape patterns.

In one embodiment, a method includes determining, by a processor, a measurement of edge detection noise; receiving a measurement of a biased parameter including measurement noise; based on the measurement of edge detection noise and a number of measurement points, determining a contribution of edge detection noise to the biased parameter; determining an unbiased parameter by subtracting the contribution of noise from the biased parameter including the measurement noise; and outputting the unbiased parameter.

A method for correcting misalignments is provided. An alignment for each device of a group of devices mounted on a substrate is determined. An alignment error for the group of devices mounted on the substrate is determined based on the respective alignment for each device. One or more correction factors are calculated based on the alignment error. The alignment error is corrected based on the one or more correction factors.

According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.

Methods for patterning a substrate are described. A substrate is scanned using a spatial light modulator with a plurality of exposures timed according to a non-crystalline shot pattern. Lithography systems for performing the substrate patterning method and non-transitory computer-readable medium for executing the patterning method are also described.

Some implementations described herein provide an exposure tool and associated methods of operation in which a scanner control system generates a scanner route for an exposure recipe such that the distance traveled by a substrate stage of the exposure tool along the scanner route is reduced and/or optimized for non-exposure fields on a semiconductor substrate. In this way, the scanner control system increases the productivity of the exposure tool, reduces processing times of the exposure tool, and increases yield in a semiconductor fabrication facility in which the exposure tool is included.

In order to provide a lithography information processing apparatus that can optimize, for example, adjustment of alignment at an outer circumferential part of a substrate, the lithography information processing apparatus includes a display control unit that causes a layout of a shot region of the substrate used in a lithography apparatus to be displayed and causes a position of an effective chip in each of the shot regions to be displayed according to the number of chips included in each of the shot regions.

A method of generating a layout pattern includes determining a first energy density indirectly exposed to a first feature of one or more features of a layout pattern on an energy-sensitive material when the one or more features of the layout pattern on the energy-sensitive material are directly exposed by a charged particle beam. The method also includes adjusting a second energy density exposed the first feature when the first feature is directly exposed by the charged particle beam. A total energy density of the first feature that comprises a sum of the first energy density from the indirect exposure and the second energy density from the direct exposure is maintained at about a threshold energy level to fully expose the first feature in the energy-sensitive material.

A method and a device for correcting a placement error of a photomask are provided. The method includes: acquiring an exposure offset during a wafer exposure after photomask manufacture is completed, wherein the wafer exposure is a process of forming a circuit pattern on a wafer surface by exposure; and determining a compensation offset for subsequent photomask manufacture according to the exposure offset, to correct a placement error of a photomask, wherein the compensation offset and the exposure offset are vector values that are equal in value and opposite in direction. The method and device for correcting the placement error of the photomask provided in the embodiments of the present disclosure can reduce an overlay error existing in a photolithography process of a semiconductor device by correcting a placement error of a photomask.

A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.