Provided is a method of fabricating a micro-nano structure, including: forming a reflective layer and a fluid polymer layer sequentially on a surface of a substrate; pressurizing the substrate and a mask having a micro-nano pattern to attach to each other, squeezing the fluid polymer layer into a light-transmission area of the mask, and curing the fluid polymer layer; and exposing, wherein a fluid polymer in the light-transmission area is configured to sense light under a combined effect of a transmitted light and a light reflected by the reflective layer, such that a micro-nano structure is obtained. The method solves the problem of limited diffraction, improves the processing resolution by reducing the transmission loss of evanescent waves through reflective light field enhancement, and reduces the difficulty and cost of mask processing and pattern defects by using shallow pressurizing in combination with exposure.

A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.

A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.

A mask layout design method capable of quickly and effectively designing a crack-resistant mask layout in a full-chip scale, a mask manufacturing method including the mask layout design method, and a mask layout are provided. The mask layout design method includes designing a full-chip layout with respect to a mask; extracting a representative pattern from the full-chip layout; detecting a stress weak point in the representative pattern; verifying the stress weak point by forming a pattern on a wafer; and changing a design rule with respect to the full-chip layout.

In a method executed in an exposure apparatus, a focus control effective region and a focus control exclusion region are set based on an exposure map and a chip area layout within an exposure area. Focus-leveling data are measured over a wafer. A photo resist layer on the wafer is exposed with an exposure light. When a chip area of a plurality of chip areas of the exposure area is located within an effective region of a wafer, the chip area is included in the focus control effective region, and when a part of or all of a chip area of the plurality of chip areas is located on or outside a periphery of the effective region of the wafer, the chip area is included in the focus control exclusion region In the exposing, a focus-leveling is controlled by using the focus-leveling data measured at the focus control effective region.

An electronic device includes a substrate having contact pads disposed thereon and traces interconnecting the contact pads. A first integrated circuit (IC) die is mounted on the substrate and includes a predefined set of circuit components arranged on the first IC die in a first geometrical pattern, which is non-symmetrical under reflection about a given axis in a plane of the die. A second IC die is mounted on the substrate and includes the predefined set of circuit components arranged on the second IC die in a second geometrical pattern, which is a mirror image of the first geometrical pattern with respect to the given axis.

A method of forming a pattern of a semiconductor device includes: preparing a semiconductor substrate including a cell region and an outer region; applying a photoresist on the semiconductor substrate; irradiating extreme ultraviolet (EUV) light reflected from an EUV mask, onto the photoresist; forming a photoresist pattern in the cell region and the outer region; and etching the semiconductor substrate, using the photoresist pattern as an etch mask. The EUV mask includes: a plurality of main patterns in a first zone, of the EUV mask, corresponding to the cell region; and a first lane and a second lane in a second zone, of the EUV mask, corresponding to the outer region, wherein the first lane and the second lane surround the plurality of main patterns, wherein the first lane has a line-and-space pattern, and the second lane has a protruding pattern.

A mask layout method includes: forming, on a mask, chip patterns arranged in an array, a scribe line being formed between every two adjacent chip patterns, the scribe line being used to provide mark patterns thereon, the mark patterns comprising at least first mark patterns; acquiring a set number of divided units of the first mark patterns; providing the set number of divided units in sequence on the scribe line so that the first mark patterns do not cover other mark patterns; and providing, on the scribe line, first mark pattern elements to replace at least two adjacent divided units, the first mark pattern elements completely overlapping patterns formed by the at least two adjacent divided units.

An arrangement apparatus includes a stage, an arrangement part, and a control part. The stage supports a substrate. The arrangement part holds a die and arranges multiple dies on the substrate supported by the stage. The control part has a map data indicating arrangement positions of the dies and generated based on a positional relationship among patterns formed by an exposure apparatus, and controls, based on the map data, relative positions between the stage and the arrangement part when arranging the dies on the substrate.

Embodiments of the present application relate to the technical field of semiconductor, and disclose a design method of a wafer layout and an exposure system of a lithography machine. The design method of a wafer layout includes: providing a yield distribution map of a wafer under an initial wafer layout; determining a yield edge position of the wafer according to the yield distribution map; and calculating a new wafer layout according to a die size and the yield edge position.