Disclosed are techniques for correcting the EUV crosstalk effects. Isolated mask feature component diffraction signals associated with individual layout feature components are determined based on a component-based mask diffraction modeling method such as a domain decomposition method. Mask feature component diffraction signals are then determined based on the isolated mask feature component diffraction signals, layout data and predetermined crosstalk signals. Here, the predetermined crosstalk signals are derived based on mask feature component diffraction signals computed using an electromagnetic field solver and the component-based mask diffraction modeling method, respectively. The mask feature component diffraction signals are then used to process layout designs.

A pattern correction amount calculating apparatus includes: an accepting unit that accepts pattern information; a micro side group acquiring unit that acquires a micro side group, which is a group of continuous sides forming a contour of a pattern figure indicated by the pattern information, and is a group of micro sides that are each small enough to satisfy a predetermined condition; a virtual side acquiring unit that acquires a virtual side, which is a side that approximates micro sides contained in the micro side group; a virtual side correction amount calculating unit that calculates a virtual side correction amount, which is a correction amount for the virtual side; and a micro side correction amount calculating unit that calculates micro side correction amounts, which are correction amounts respectively for the micro sides contained in the micro side group corresponding to the virtual side, using the virtual side correction amount.

The present disclosure relates generally to cleaning compositions and, more specifically, to cleaning compositions containing an etheramine that is suitable for removal of stains from soiled materials.

A method of manufacturing a mask may include identifying an error pattern of final patterns formed on a substrate, correcting a first target pattern on the basis of the error pattern, fracturing a first mask layout into a plurality of first segments on the basis of the corrected first target pattern, and correcting the first mask layout by biasing a plurality of first target segments corresponding to a first final target among the plurality of segments. The first mask layout may include a first extension pattern, final targets disposed in zigzags, and the first final target corresponding to the error pattern, and each of the plurality of first segments may corresponds to one of the final targets.

A method involving obtaining a simulation of a contour of a pattern to be formed on a substrate using a patterning process, determining a location of an evaluation point on the simulated contour of the pattern, the location spatially associated with a location of a corresponding evaluation point on a design layout for the pattern, and producing electronic information corresponding to a spatial bearing between the location of the evaluation point on the simulated contour and the location of the corresponding evaluation point on the design layout, wherein the information corresponding to the spatial bearing is configured for determining a location of an evaluation point on a measured image of at least part of the pattern, the evaluation point on the measured image spatially associated with the corresponding evaluation point on the design layout.

A method, system, and computer program product for triple patterning technology (TPT) violation detection and visualization within an integrated circuit design layout are disclosed. In a first aspect, the method comprises mapping a plurality of violations of the integrated circuit design layout to a graph, generating a color graph corresponding to the graph, detecting at least one TPT violation from the color graph; and visualizing the at least one TPT violation on a layout canvas. In a second aspect, the system comprises a graph generator module for mapping a plurality of violations of the integrated circuit design layout to a graph and to generate a color graph corresponding to the graph, a detector module for detecting at least one TPT violation from the color graph, and a visualizer module for visualizing the at least one TPT violation on a layout canvas.

An extreme ultraviolet lithography (EUVL) method includes providing at least two phase-shifting mask areas having a same pattern. A resist layer is formed over a substrate. An optimum exposure dose of the resist layer is determined, and a latent image is formed on a same area of the resist layer by a multiple exposure process. The multiple exposure process includes a plurality of exposure processes and each of the plurality of exposure processes uses a different phase-shifting mask area from the at least two phase-shifting mask areas having a same pattern.

Manufacturing of semiconductor devices often involves performed photolithography to pattern and etch the various features of those devices. Such photolithography involves masking and focusing light onto a surface of the semiconductor device for exposing and etching the features of the semiconductor devices. However, due to design specifications and other causes, the semiconductor devices may not have a perfectly flat light-incident surface. Rather, some areas of the semiconductor device may be raised or lowered relative to other areas of the semiconductor device. Therefore, focusing the light on one area causes another to become unfocused. By carefully designing a photomask to cause phase shifts of the light transmitted therethrough, focus across all areas of the semiconductor device can be achieved during photolithography, which results in sharp and accurate patterns formed on the semiconductor device.

A pattern of features of an integrated circuit is provided. A configuration of a pupil of an extreme ultraviolet wavelength radiation beam (also referred to as an illumination mode), is selected. The selected configuration is an asymmetric, single pole configuration. At least one disparity is determined between a simulated imaging using the selected configuration and a designed imaging for the pattern of features. A parameter (also referred to as a compensation parameter) is then modified to address the at least one disparity, wherein the parameter at least one a design feature, a mask feature, and a lithography process parameter. A substrate is then exposed to the pattern of features using the selected configuration and the modified parameter.

A computer-implemented method of designing an integrated circuit (IC) includes allocating a plurality of colors to a plurality of patterns corresponding to one layer of a first cell so that a multi-patterning technology is designated for use in forming the plurality of patterns, the first cell being a multi-height cell corresponding to a plurality of rows, generating a plurality of shift cells, in which a color remapping operation associated with the plurality of patterns is performed for each row, with respect to the first cell, and storing a cell set including the first cell and the plurality of shift cells in a standard cell library.