A real-time variable parameter micro-nano optical field modulation system includes a light source, a 4F optical system and a set of light wave modulation optical components. The 4F optical system includes a first optical assembly and a second optical assembly arranged along an optical path in sequence. The light wave modulation optical components are arranged between the first optical assembly and the second optical assembly, and generate optical field distribution with adjustable patterns and structural parameters thereof on a back focal plane of the system by segmented modulation of sub-wavefronts.

An extreme ultraviolet (EUV) exposure system capable of improving the yield of an EUV exposure process by improving EUV exposure performance, and furthermore, capable of increasing throughput or productivity of the EUV exposure process, the EUV exposure system including an EUV exposure apparatus configured to perform EUV exposure on a wafer disposed on a chuck table, a load-lock chamber combined with the EUV exposure apparatus and configured to supply and discharge the wafer to/from the EUV exposure apparatus, and an ultraviolet (UV) exposure apparatus configured to perform UV exposure by irradiating an entire upper surface of the wafer with a UV light without using a mask.

In some embodiments, the present disclosure relates a lithographic substrate marking tool. The lithographic substrate marking tool has a first lithographic exposure tool arranged within a shared housing and configured to generate a first type of electromagnetic radiation during a plurality of exposures. A mobile reticle has a plurality of different reticle fields respectively configured to block a portion of the first type of electromagnetic radiation to expose a substrate identification mark within a photosensitive material overlying a semiconductor substrate. A transversal element is configured to move the mobile reticle so that separate ones of the plurality of reticle fields are exposed onto the photosensitive material during separate ones of the plurality of exposures. The mobile reticle therefore allows for different strings of substrate identification marks to be formed within the photoresistive material using a same reticle, thereby economically providing the benefits of lithographic substrate marking.

Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a method of data compression or data reduction for e-beam tool simplification involves providing an amount of data to write a column field and to adjust the column field for field edge placement error on a wafer, wherein the amount of data is limited to data for patterning approximately 10% or less of the column field. The method also involves performing e-beam writing on the wafer using the amount of data.

The present invention provides a method for multiscale patterning of a sample. The method includes: placing the sample in an apparatus having both thermo-optical lithography capability and thermal scanning probe lithography capability; and patterning two patterns onto the sample, respectively by: thermo-optical lithography, wherein light is emitted from a light source onto the sample to heat the latter and thereby write a first pattern that is the largest of the two patterns; and thermal scanning probe lithography, wherein the sample and a heated probe tip are brought in contact for writing a second pattern that has substantially smaller critical dimensions than the first pattern. There is also provided an apparatus for multiscale patterning of a sample.

The present embodiments relate to MP electroplating processes that eliminate seamlines using a bottom-up MP electroplating process. The MP electroplating process can include, after disposing the side shield, depositing a Ru layer as a side gap layer. The process can further include depositing an insulator layer. The MP bottom-up electroplating process can further include performing an ion-beam-etch (IBE) process to clean the insulator at bottom of the trench. After resist patterning, the electroplating process can include electroplating the MP on Ru seed only from the bottom of the trench. The seamline in the MP can be eliminated in the bottom-up MP electroplating process.

A method of forming patterns includes forming an etch target film on a substrate having a first region and a second region, forming a hardmask structure on the etch target film in the first region and the second region, the hardmask structure including a plurality of hardmask layers, forming a first photoresist film on the hardmask structure in at least one of the first region and the second region, forming a first photoresist pattern in the second region by exposing and developing the first photoresist film, and forming a pattern from the etch target film by etching the hardmask structure and the etch target film by using the first photoresist pattern, wherein a top surface of the hardmask structure in the first region is exposed to the outside after the first photoresist film is developed.

A photoresist composition includes an organometallic compound including at least one metal-ligand bond and having an absorbance to first light, the at least one metal-ligand bond including a metal core and at least one organic ligand bonded to the metal core, a photosensitive additive having an absorbance to second light having a longer wavelength than the first light, and a solvent. A method of manufacturing an integrated circuit device includes forming a photoresist film on a substrate based on using the photoresist composition, exposing a first area of the photoresist film to the first light, exposing an entire area of the photoresist film to the second light, and forming a network of metal structures in the first area based on baking the photoresist film.

A semiconductor processing system includes a first photolithography system and a second photolithography system. The semiconductor processing system includes a layout database that stores a plurality of layouts indicating features to be formed in a wafer. The semiconductor processing system includes a layout analyzer that analyzes the layouts and selects either the first photolithography system or the second photolithography system based on dimensions of features in the layouts.

A semiconductor processing system includes a first photolithography system and a second photolithography system. The semiconductor processing system includes a layout database that stores a plurality of layouts indicating features to be formed in a wafer. The semiconductor processing system includes a layout analyzer that analyzes the layouts and selects either the first photolithography system or the second photolithography system based on dimensions of features in the layouts.