Techniques and arrangements for performing exposure operations on a wafer utilizing both a stepper apparatus and an aligner apparatus. The exposure operations are performed with respect to large composite base dies, e.g., interposers, defined within the wafer, where the interposers will become a part of microelectronic devices by coupling with active dies or microchips. The composite base dies may be coupled to the active dies via “native interconnects” utilizing direct bonding techniques. The stepper apparatus may be used to perform exposure operations on active regions of the composite base dies to provide a fine pitch for the native interconnects, while the aligner apparatus may be used to perform exposure operations on inactive regions of the composite base dies to provide a coarse pitch for interfaces with passive regions of the composite base dies.

The invention relates to a method for producing a structure in a lithographic material, wherein the structure in the lithographic material is defined by means of a writing beam of an exposure device, in that a plurality of partial structures are written sequentially, wherein for writing the partial structures a write field of the exposure device is displaced and positioned sequentially and that a partial structure is written in the write field in each case, and wherein for positioning of the write field a reference structure is detected by means of an imaging measuring device. For calibration of the write field in the respectively positioned write field, before, during or after writing a partial structure, at least one reference structure element assigned to this partial structure is produced in the lithographic material with the writing beam, wherein the reference structure element after the displacement of the write field is detected by means of the imaging measuring device for writing a further partial structure.

A method of reducing image placement errors in a microlithographic projection exposure apparatus includes providing a mask, a light sensitive layer and a microlithographic projection exposure apparatus which images features of the mask onto the light sensitive surface using projection light. Subsequently, image placement errors associated with an image of the features formed on the light sensitive surface are determined either by simulation or metrologically. Then an input state of polarization of the projection light is changed to an elliptical output state of polarization which is selected such that the image placement errors are reduced.

A digital exposure apparatus includes a lens array, the lens array at least including a first lens unit and a second lens unit, a light transposition assembly arranged on an exit light path of the second lens unit, and the light transposition assembly being used for controlling a light exiting from the second lens unit to be transposed with respect to an exposure direction of the digital exposure apparatus. When the digital exposure apparatus is used for exposure, a light passing through the first lens unit and a light penetrating through the second lens unit are needed to expose the same position for multiple times.

A method of processing a wafer is provided. The method includes providing a reference pattern for patterning a wafer. The reference pattern is independent of a working surface of the wafer. A placement of a first pattern on the working surface of the wafer is determined by identifying the reference pattern to align the first pattern. The first pattern is formed on the working surface of the wafer based on the placement.

The present disclosure relates generally to cleaning compositions and, more specifically, to cleaning compositions containing an etheramine that is suitable for removal of stains from soiled materials.

A method, system, and computer program product for triple patterning technology (TPT) violation detection and visualization within an integrated circuit design layout are disclosed. In a first aspect, the method comprises mapping a plurality of violations of the integrated circuit design layout to a graph, generating a color graph corresponding to the graph, detecting at least one TPT violation from the color graph; and visualizing the at least one TPT violation on a layout canvas. In a second aspect, the system comprises a graph generator module for mapping a plurality of violations of the integrated circuit design layout to a graph and to generate a color graph corresponding to the graph, a detector module for detecting at least one TPT violation from the color graph, and a visualizer module for visualizing the at least one TPT violation on a layout canvas.

Techniques related to multi-pass patterning lithography, device structures, and devices formed using such techniques are discussed. Such techniques include exposing a resist layer disposed over a grating pattern with non-reflecting radiation to generate an enhanced exposure portion within a trench of the grating pattern and developing the resist layer to form a pattern layer having a pattern structure within the trench of the grating pattern.

An extreme ultraviolet lithography (EUVL) method includes providing at least two phase-shifting mask areas having a same pattern. A resist layer is formed over a substrate. An optimum exposure dose of the resist layer is determined, and a latent image is formed on a same area of the resist layer by a multiple exposure process. The multiple exposure process includes a plurality of exposure processes and each of the plurality of exposure processes uses a different phase-shifting mask area from the at least two phase-shifting mask areas having a same pattern.

An apparatus comprises a low EUV reflectivity (LEUVR) mask. The LEUVR mask includes a low thermal expansion material (LTEM) layer; a reflective multilayer (ML) over the LTEM layer; and a patterned absorption layer over the reflective ML. The reflective ML has less than 2% EUV reflectivity.