Methods for manufacturing a semiconductor structure are provided. A substrate is provided. A metrology target is formed in a layer over the substrate according to a first layer mask and a second layer mask. The metrology target includes a first pattern formed by a plurality of first photonic crystals corresponding to the first layer mask and a second pattern formed by a plurality of second photonic crystals corresponding to the second layer mask. First light is provided to illuminate the metrology target. Second light is received from the metrology target in response to the first light. The second light is analyzed to detect overlay-shift between the first pattern and the second pattern. The first pattern and the second pattern are arranged to cross in one direction in the metrology target.

Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Overlay-shift measurement systems are provided. An overlay-shift measurement system includes an optical device, a first light detection device and a processor. The optical device is configured to provide an input light to a metrology target of a semiconductor structure. The first light detection device is configured to receive a transmitted light from the metrology target when the input light penetrates the metrology target. The processor is configured to determine whether overlay-shift between a plurality of first photonic crystals and a plurality of second photonic crystals in the metrology target is present according to characteristics of the transmitted light.

Techniques and arrangements for performing exposure operations on a wafer utilizing both a stepper apparatus and an aligner apparatus. The exposure operations are performed with respect to large composite base dies, e.g., interposers, defined within the wafer, where the interposers will become a part of microelectronic devices by coupling with active dies or microchips. The composite base dies may be coupled to the active dies via “native interconnects” utilizing direct bonding techniques. The stepper apparatus may be used to perform exposure operations on active regions of the composite base dies to provide a fine pitch for the native interconnects, while the aligner apparatus may be used to perform exposure operations on inactive regions of the composite base dies to provide a coarse pitch for interfaces with passive regions of the composite base dies.

A lithography method to pattern a first semiconductor wafer is disclosed. An optical mask is positioned over the first semiconductor wafer. A first region of the first semiconductor wafer is patterned by directing light from a light source through transparent regions of the optical mask. A second region of the first semiconductor wafer is patterned by directing energy from an energy source to the second region, wherein the patterning of the second region comprises direct-beam writing.

Embodiments of the present application provide an integrated circuit structure formation method, including: providing a first pattern and a to-be-corrected pattern, the first pattern including a first subpattern and a second subpattern spaced apart, the to-be-corrected pattern being located between the first subpattern and the second subpattern, and a preset horizontal distance being provided between the first pattern and the to-be-corrected pattern; providing a trim mask, the trim mask having a preset region, in a plane including the to-be-corrected pattern, a first orthographic projection of the preset region overlapping with the to-be-corrected pattern, a second orthographic projection being located on one side of the to-be-corrected pattern, and a horizontal length being greater than or equal to twice the preset horizontal distance; and performing an exposure process through the trim mask to form a target pattern. The embodiments of the present application facilitate accurate trimming of the to-be-corrected pattern.

A photomask assembly includes: a first photomask for forming a first patterned structure, the first patterned structure having a first patterned opening which includes a plurality of strip-shaped patterns, a distance between the strip-shaped patterns at the two sides of a boundary between the first region and the second region being greater than a distance between other every two neighboring strip-shaped patterns when the center of the first photomask coincides with the center of the substrate; and a second photomask for forming a second patterned region which covers a first patterned opening of a second region, a distance between an opening edge of the second patterned structure and the neighboring strip-shaped pattern being greater than a first preset distance when the center of the second photomask and the center of the first photomask coincide with the center of the substrate.

The present disclosure relates generally to cleaning compositions and, more specifically, to cleaning compositions containing an etheramine that is suitable for removal of stains from soiled materials.

A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.

A photolithography patterning stack and method for repairing defects in the stack. The stack includes an organic planarization layer, a hardmask layer, and a plurality of patterned photoresist lines in contact with the hardmask layer. A plurality of trenches is situated between the plurality of patterned photoresist lines. Each trench exposes a portion of the hardmask layer. A repairing layer is formed in contact with and only bonded to surfaces of the plurality of patterned photoresist lines. The method includes forming a photolithographic patterning stack. The stack includes at least a hardmask layer formed on one or more underlayers and a photoresist layer formed in contact with the hardmask layer. The photoresist layer is patterned into a plurality of patterned portions. A repairing layer is formed in contact with and only bonded to surfaces of each patterned portion of the plurality of portions.