This invention provides an exposure apparatus for exposing each of a plurality of shot regions on a substrate. The exposure apparatus includes a control unit configured to control exposure processing of exposing each of the plurality of shot regions on the substrate using control information for controlling shapes of the shot regions exposed on the substrate such that the plurality of shot regions are adjacent to each other. The control information includes correction information for correcting, based on layout information of a plurality of shots adjacent to each other, a shift of adjacent portions of the plurality of shot regions caused by a distortion of the shapes of the plurality of shot regions. The control unit controls the exposure processing using the correction information.

A method, comprising forming a material layer over a substrate; illuminating at least one region of the material layer with a light; recording strength of the light reflected from the at least one region; and determining a thickness of the material layer in the at least one region according to the strength of the light.

A stitching method for an exposure process includes following steps. A wafer is provided. The wafer includes interposer regions, each of which includes a logic chip region, a first memory chip region, and a second memory chip region. The logic chip region is located between the first and second memory chip regions. A photoresist layer is formed on the wafer. First exposure processes are performed on the photoresist layer by applying a first photomask to form first shot regions in the photoresist layer. Second exposure processes are performed on the photoresist layer by applying a second photomask to form second shot regions in the photoresist layer. The first shot regions and the second shot regions are arranged alternately in a first direction. The first shot regions and the second shot regions are overlapped to form stitching regions, each of which is not located in the logic chip region.

In an exposure method of performing a scan exposure of a substrate, held by a substrate stage, in a first direction for each shot region, a surface position of an exposure area is pre-measured before the exposure area reaches a region, to be irradiated with exposure light, of the substrate, movement of the substrate stage in order to change a shot region to undergo the scan exposure includes first movement in which the substrate stage moves along a curved trajectory, and second movement in which the substrate stage rectilinearly moves in the first direction, and, while the movement of the substrate stage is the first movement, the surface position is pre-measured, and a pre-measure position in a shot region is common among a plurality of shot regions.

The present application discloses an image stitching method for a stitching product, which includes: step 1: providing a chip design layout of the stitching product; step 2: designing a mask layout according to the chip design layout, including: step 21: setting unit mask images; step 22: merging logic images or cutting path images of adjacent areas between unit regions together to set corresponding peripheral mask images; step 23: merging the same peripheral mask images into one; step 24: constituting a mask layer by using the unit mask images and each peripheral mask image, and forming the mask layout on a mask; step 3: performing repeated exposure to form the stitching product. The present application can reduce the number of mask images, the number of times of exposure and the time of exposure.

The present application discloses a method for measuring stitching overlay accuracy of image sensor stitching manufacturing, forming an A-type overlay pattern mark and a corresponding B-type overlay pattern mark on the edge of each rectangular pixel area to be stitched; after the A-type overlay pattern mark and the B-type overlay pattern mark are stitched and exposed, performing metrology by means of a scanning electron microscope to obtain dimension features; and according to the dimension features of the A-type overlay pattern mark and the B-type overlay pattern mark stitched together and exposed and measured by the scanning electron microscope, determining stitching overlay accuracy of two adjacent rectangular pixel areas. The present application can achieve direct metrology on the overlay pattern mark on the stitched pixel area of a product, facilitating timely and accurate monitoring on the stitching overlay accuracy of image sensor stitching manufacturing.

Embodiments of the present disclosure provide an interposer and a method of forming the same, and the method includes: providing a baseplate; forming a pattern transfer layer including a plurality of pattern regions spliced together on the baseplate, different pattern regions correspond to different lithographic templates, a splicing region of at least two pattern regions is an overlapping region, and any one of the lithographic templates includes a pattern composed of an exposed region for exposure and a masked region for masking; preprocessing the pattern transfer layer so that the plurality of pattern regions of the pattern transfer layer have different etching selectivity ratios in corresponding exposed regions and masked regions based on patterns of corresponding lithographic templates; etching the pattern transfer layer after preprocessed to form the patterns of corresponding lithographic templates on the pattern transfer layer; patterning the baseplate using the pattern transfer layer as a mask.

A first bright field reticle and a second bright field reticle are utilized for a double exposure EUV photolithography process in which exposure areas of the first and second bright field reticles overlap. The first and second reticles each include, respectively, a substrate, a reflective multilayer on the substrate, a main pattern of absorption material on the reflective multilayer, a black border area, and an additional absorption area of the absorption material between the black border and the main pattern.

A first bright field reticle and a second bright field reticle are utilized for a double exposure EUV photolithography process in which exposure areas of the first and second bright field reticles overlap. The first and second reticles each include, respectively, a substrate, a reflective multilayer on the substrate, a main pattern of absorption material on the reflective multilayer, a black border area, and an additional absorption area of the absorption material between the black border and the main pattern.

A system, methods, and a non-transitory computer-readable medium for digital lithography to reduce mura in substrate sections. The boundary lines of the digital lithography need to be invisible. In one example, a system includes a processing unit configured to print a virtual mask file provided by a controller. The controller is configured to receive data and convert the data into a virtual mask file having an exposure pattern for a lithographic process. The exposure pattern includes a plurality of first sections, and second sections. Each first section forms a boundary with each second section along a first column of image projection systems of the processing unit. The controller patterns the substrate. The exposure pattern includes a first section pattern of each first section that crosses the eye to eye boundary with the second section making the boundary invisible.