A photomask according to an exemplary embodiment includes: a mask substrate; and a first test pattern and a second test pattern disposed along a first edge of the mask substrate, wherein the first test pattern has a first outer shape and a first inner shape, the second test pattern has a second outer shape, and the second outer shape of the second test pattern is larger than the first inner shape of the first test pattern and smaller than the first outer shape of the first test pattern.

Techniques are described for fabricating integrated circuit devices that span multiple reticle fields. Integrated circuits formed within separate reticle fields are placed into electrical contact with each other by overlapping reticle fields to form an overlapping conductive interconnect. This overlapping conductive interconnect electrically connects an interconnect layer of a first reticle field with an interconnect layer of a second, laterally adjacent reticle field. The overlapping conductive interconnection extends into a common scribe zone between adjacent reticle fields.

A lithography system for generating grating structures is provided having a multiple column imaging system located on a bridge capable of moving in a cross-scan direction, a mask having a grating pattern with a fixed spatial frequency located in an object plane of the imaging system, a multiple line alignment mark aligned to the grating pattern and having a fixed spatial frequency, a platen configured to hold and scan a substrate, a scanning system configured to move the platen over a distance greater than a desired length of the grating pattern on the substrate, a longitudinal encoder scale attached to the platen and oriented in a scan direction and at least two encoder scales attached to the platen and arrayed in the cross-scan direction wherein the scales contain periodically spaced alignment marks having a fixed spatial frequency.

A system and method for fabricating distinct types of circuit connections on a semiconductor wafer includes fabricating, using a first photomask, a plurality of a first type of circuit connections for each of a plurality of distinct die of a semiconductor wafer; and fabricating, using a second photomask, a plurality of a second type of circuit connections between a plurality of distinct pairs of components of the semiconductor wafer, wherein each distinct pair of components includes at least one distinct die of the plurality of distinct die and one of a conductive pad and a sacrificial die.

A device and method for producing light-exposed structures on a workpiece having a light-sensitive surface. An optical unit includes a light source and a diffraction grating for producing a strip-shaped illumination pattern having strips extending in a longitudinal direction and having a pattern width extending transversely. A device moves the surface of the workpiece and optical unit relative to each other according to a path sequence, which includes movement longitudinal paths to produce a first and second light-exposed structure having strips, which is oriented parallel to each other on the workpiece surface. The movement paths are mutually spaced apart by less than the pattern width and the light-exposed structures overlap in such a way that strips of the light-exposed structures lie on each other. To obtain good light exposure of the surface by the illumination pattern, the diffraction grating is set oblique to the surface of the workpiece that is light-exposed by the illumination pattern.

Embodiments of the present disclosure provide improved photolithography systems and methods using a solid state emitter device. The solid state emitter device includes an array of solid state emitters arranged in a plurality of horizontal rows and vertical columns. The variable intensity of each group of solid state emitters, for example an entire row or column of solid state emitters, is controllable for improved field brightness uniformity and stitching. Controlling the variable intensity includes, for example, varying the signal, such as voltage, that is applied to each of the rows of solid state emitters to attenuate the brightness from the middle of the array to the edges of the array to accommodate for overlapping exposures during photolithography processing.

In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

A system, software application, and method for optical device metrology of optical device patterns formed from lithography stitching are provided. In one example, the method includes creating a stitched design file comprising images of a plurality of masks; defining target coordinates for each of the plurality of masks in the stitched design file; defining an alignment mark for the stitched design file; capturing images of an optical device pattern at each of the target coordinates; comparing the captured images of the optical device pattern at each of the target coordinates to virtual images of the stitched design file at each of the target coordinates; and determining whether the optical device pattern at each of the target coordinates meets a threshold value.

A system and method for fabricating distinct types of circuit connections on a semiconductor wafer includes fabricating, using a first photomask, a plurality of a first type of circuit connections for each of a plurality of distinct die of a semiconductor wafer; and fabricating, using a second photomask, a plurality of a second type of circuit connections between a plurality of distinct pairs of components of the semiconductor wafer, wherein each distinct pair of components includes at least one distinct die of the plurality of distinct die and one of a conductive pad and a sacrificial die.

A method of forming patterned features on a substrate is provided. The method includes positioning a plurality of masks arranged in a mask layout over a substrate. The substrate is positioned in a first plane and the plurality of masks are positioned in a second plane, the plurality of masks in the mask layout have edges that each extend parallel to the first plane and parallel or perpendicular to an alignment feature on the substrate, the substrate includes a plurality of areas configured to be patterned by energy directed through the masks arranged in the mask layout. The method further includes directing energy towards the plurality of areas through the plurality of masks arranged in the mask layout over the substrate to form a plurality of patterned features in each of the plurality of areas.