A method of manufacturing a photomask including the steps of receiving initial photomask design data associated with one or more patterns to be formed on a photomask and optimizing the initial photomask design data to minimize printing exposure energy while maintaining an acceptable pattern quality and size. In embodiments, the step of optimizing includes setting minimization of printing exposure energy as a priority design rule, setting optimization of pattern quality and size as a secondary design rule, iterating size of mask design features to determine a range of size biases that satisfy both the priority and secondary design rules so as to provide an initial optimized mask design, and adjusting mask variables over the range of size biases to determine mask variables that further optimize the initial optimized mask design to obtain a final optimized mask design.

A method for determining a correction relating to a performance metric of a semiconductor manufacturing process, the method including: obtaining a set of pre-process metrology data; processing the set of pre-process metrology data by decomposing the pre-process metrology data into one or more components which: a) correlate to the performance metric; or b) are at least partially correctable by a control process which is part of the semiconductor manufacturing process; and applying a trained model to the processed set of pre-process metrology data to determine the correction for the semiconductor manufacturing process.

A method is described for creating a modified mask with low surface energies for a nano-imprint lithography (NIL) imprinting process. The method includes applying a master mold to an imprint mask material to create an imprint mask. The method further includes modifying the imprint mask by applying a treatment to the imprint mask to cause a surface energy level of the imprint mask to fall below a sticking threshold. The modified imprint mask is applied to a nano-imprint lithography (NIL) material to create an imprinted NIL material layer. The surface energy level of the imprint mask causes a shape of the imprinted NIL material layer to be remain unchanged when the imprinted NIL material layer is detached from the modified imprint mask.

An exposure apparatus arranged to project a radiation beam onto a target portion of a substrate, the exposure apparatus having: a first substrate holder configured to hold the substrate; a second substrate holder configured to hold the substrate; a sensor holder configured to hold a sensor and/or detector; a first measurement device having a first alignment system having an alignment sensor configured to measure positions of a substrate alignment mark on the substrate; a second measurement device having a second alignment system having a further alignment sensor configured to measure positions of the substrate alignment mark on the substrate; a first scale arranged on a lower surface of the first substrate holder; and a first encoder head arranged to cooperate with the first scale, the first encoder head located beneath the first alignment system and held by a stationary support.

A method of optimizing an apparatus for multi-stage processing of product units such as wafers, the method includes: receiving object data representing one or more parameters measured across the product units and associated with different stages of processing of the product units; and determining fingerprints of variation of the object data across the product units, the fingerprints being associated with different respective stages of processing of the product units. The fingerprints may be determined by decomposing the object data into components using principal component analysis for each different respective stage; analyzing commonality of the fingerprints through the different stages to produce commonality results; and optimizing an apparatus for processing product units based on the commonality results.

The invention provides a light source optimization apparatus including a storage apparatus and a processor. The storage apparatus stores a plurality of modules. The processor is coupled to the storage apparatus and configured to execute the plurality of modules. The plurality of modules include a critical pattern module and a light source optimization module. The critical pattern module retrieves critical pattern data. The light source optimization module executes an ant colony optimization (ACO) algorithm according to a preset parameter to adjust an initial light source image to generate an output light source image, and the initial light source image corresponds to the critical pattern data.

Methods and apparatus for classifying semiconductor wafers. The method can include: sorting a set of semiconductor wafers, using a model, into a plurality of sub-sets based on parameter data corresponding to one or more parameters of the set of semiconductor wafers, wherein the parameter data for semiconductor wafers in a sub-set include one or more common characteristics; identifying one or more semiconductor wafers within a sub-set based on a probability of the one or more semiconductor wafers being correctly allocated to the sub-set; comparing the parameter data of the one or more identified semiconductor wafers to reference parameter data; and reconfiguring the model based on the comparison. The comparison is undertaken by a human to provide constraints for the model. The apparatus can be configured to undertake the method.

Disclosed is a method of determining calibrated reference exposure and measure grids for referencing position of a substrate stage in a lithographic system. The method comprises obtaining calibration data relating to one or more calibration substrates; and determining an exposure grid for an exposure side of the lithographic system from said calibration data and a measure grid for a measure side of the lithographic system from said calibration data. The exposure grid and said measure grid are decomposed so as to remove a calibration substrate dependent component from said exposure grid and from said measure grid to obtain a substrate independent exposure grid and substrate independent measure grid.

According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.

According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.