In a method executed in an exposure apparatus, a focus control effective region and a focus control exclusion region are set based on an exposure map and a chip area layout within an exposure area. Focus-leveling data are measured over a wafer. A photo resist layer on the wafer is exposed with an exposure light. When a chip area of a plurality of chip areas of the exposure area is located within an effective region of a wafer, the chip area is included in the focus control effective region, and when a part of or all of a chip area of the plurality of chip areas is located on or outside a periphery of the effective region of the wafer, the chip area is included in the focus control exclusion region In the exposing, a focus-leveling is controlled by using the focus-leveling data measured at the focus control effective region.

In a beam irradiation apparatus in which a movable body holds an object, a mark detection system detects a first mark on the movable body while moving the movable body in a first direction and changing an irradiation position of a measurement beam in the first direction, the mark detection system detects a second mark while moving the movable body in the first direction and changing the irradiation position of the measurement beam in the first direction, a controller controls a position of the movable body in a second direction intersecting the first direction during a time period between the detection of the first mark and the detection of the second mark, and the controller controls the movement of the movable body to adjust a positional relation between the object on the movable body and a processing beam, based on results of the detection of the first and second marks.

A structure of a semiconductor device with a sub-segmented grating structure as a metrology mark and a method for configuring the metrology mark. The method for configuring a metrology mark may be used in a lithography process. The method may include determining an initial characteristic function of an initial metrology mark disposed within a layer stack. The method also includes perturbing one or more variables of the plurality of subsegments of the metrology mark (e.g., pitch, duty cycle, and/or line width of the plurality of subsegments) and further perturbing a thickness of one or more layers within the layer stack. The method further includes iteratively performing the perturbations until a minimized characteristic function of an initial metrology mark is determined to set a configuration for the plurality of subsegments.

The present invention provides a processing system that includes a first apparatus and a second apparatus, and processes a substrate, wherein the first apparatus includes a first measurement unit configured to detect a first structure and a second structure different from the first structure provided on the substrate, and measure a relative position between the first structure and the second structure, and the second apparatus includes an obtainment unit configured to obtain the relative position measured by the first measurement unit, a second measurement unit configured to detect the second structure and measure a position of the second structure, and a control unit configured to obtain a position of the first structure based on the relative position obtained by the obtainment unit and the position of the second structure measured by the second measurement unit.

A control apparatus for generating a control signal for controlling a control target includes a plurality of neural networks, and a selector configured to select, from the plurality of neural networks, a neural network to be used to generate the control signal, wherein each of the plurality of neural networks is selected by the selector to be used in execution of one corresponding control pattern among a plurality of control patterns for controlling the control target.

A method of processing a wafer is provided. The method includes providing a reference plate below the wafer. The reference plate includes a reference pattern. The reference plate is imaged to capture an image of the reference pattern by directing light through the wafer. A first pattern is aligned using the image of the reference pattern. The first pattern is applied to a working surface of the wafer based on the aligning.

An information processing apparatus includes an acquisition unit configured to acquire process information about a substrate process, the process information including process data and a process condition, and a display control unit configured to control a display on a display apparatus based on the process information acquired by the acquisition unit, wherein the display control unit selectively displays, on the display apparatus, a first screen that displays the process data of a lot including a plurality of substrates on a lot-by-lot basis and a second screen that displays the process data of a first lot on a substrate-by-substrate basis, the first lot being a lot designated by a user from the lot displayed on the first screen.

An apparatus for and method of sensing multiple alignment marks in which the optical axis of a detector is divided into multiple axes each of which can essentially simultaneously detect a separate alignment mark to generate a signal which can then be multiplexed and presented to a single detector or multiple detectors thus permitting more rapid detection of multiple marks.

The present application provides an alignment method for backside photolithography process of the wafer, the alignment method includes: cutting the wafer, and using at least two edges formed by cutting as the first alignment mark; bonding the front side of the wafer to the wafer pad to form a composite wafer; aligning the first alignment mark with the corresponding second alignment mark on the photomask for backside photolithography. This method is not limited by wafer thickness and material, and reduces the secondary input of the photolithography equipment; meanwhile, the probability of fragments of thin wafers in the photolithography process can be reduced, and the yield of the product is effectively improved.

In a method executed in an exposure apparatus, a focus control effective region and a focus control exclusion region are set based on an exposure map and a chip area layout within an exposure area. Focus-leveling data are measured over a wafer. A photo resist layer on the wafer is exposed with an exposure light. When a chip area of a plurality of chip areas of the exposure area is located within an effective region of a wafer, the chip area is included in the focus control effective region, and when a part of or all of a chip area of the plurality of chip areas is located on or outside a periphery of the effective region of the wafer, the chip area is included in the focus control exclusion region In the exposing, a focus-leveling is controlled by using the focus-leveling data measured at the focus control effective region.