The present application provides a method for avoiding a damage to an overlay metrology mark, forming a plurality of raised silicon structures on an active area of a scribe line area on a silicon substrate, forming first to third dielectric layers on the silicon structure, and forming an axial structure of a fin and a spacer on the first to third dielectric layers; forming a shallow trench isolation (STI) area on the silicon substrate between the axial structures; removing a portion of the silicon structure along the height thereof on the scribe line area, the height of the residual silicon structure is 150-300 angstroms higher than that of the STI area; forming a plurality of dummy gates on the residual silicon structure on the scribe line, then applying a dielectric layer to fill a gap between the dummy gates, polishing the dielectric layer to expose the top of the dummy gate.

An operating method includes: placing a first mask, a second mask, a third mask and a fourth mask on a rotating base, in which each of the first, second, third and fourth masks has a first exposure unit, a second exposure unit, a third exposure unit and a fourth exposure unit; overlaying the first, second, third and fourth masks such that the first exposure unit of the first mask, the second exposure unit of the second mask, the third exposure unit of the third mask and the fourth exposure unit of the fourth mask are arranged adjacently to form an exposure area; simulating a first coordinate information according to the exposure area by an image simulation unit; scanning the exposure area, by a scanning electron microscope (SEM), to obtain a second coordinate information; and comparing the first coordinate information with the second coordinate information.

A 3D integrated circuit, the circuit including: a first level including a first wafer, the first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second level including a second wafer, the second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors, where the second level is bonded to the first level, where the bonded includes metal to metal bonding, where the bonded includes oxide to oxide bonding, and where at least one of the second transistors include a replacement gate.

The present application provides a mask applied to semiconductor photolithography and a photolithographic method, and the mask includes at least one pattern group, each pattern group including at least one light-transmitting region and at least one shielding region, the light-transmitting regions and the shielding regions being arranged at intervals, and after exposure, each pattern group forming an independent mark on a wafer. The present application has the following advantages. The independent mark formed on the wafer according to the mask has the same shape as a contour of a pattern of the mask, and does not have a pattern defect, which improves accuracy of an independent mark pattern formed on the wafer, and then alignment precision of the semiconductor photolithography as well as overlaying accuracy in a following semiconductor process, thus increasing a quality and a yield of products.

A mark detection method includes: acquiring on-off information of marks on a photomask to be manufactured; comparing the on-off information with preset on-off information to determine whether the on-off information is consistent with the preset on-off information; and, correcting the on-off information according to the preset on-off information when it is determined that the on-off information is inconsistent with the preset on-off information. The mark detection method and apparatus and the computer-readable storage medium according to the present disclosure can automatically detect whether the on-off of marks is accurate, thereby improving the detection accuracy and reducing labor cost.

An apparatus for measuring a position of a mark on a substrate, the apparatus comprising: an illumination system configured to condition at least one radiation beam to form a plurality of illumination spots spatially distributed in series such that during scanning of the substrate the plurality of illumination spots are incident on the mark sequentially, and a projection system configured to project radiation diffracted by the mark from the substrate, the diffracted radiation being produced by diffraction of the plurality of illumination spots by the mark; wherein the projection system is further configured to modulate the diffracted radiation and project the modulated radiation onto a detecting system configured to produce signals corresponding to each of the plurality of illumination spots, the signals being combined to determine the position of the mark.

An alignment system includes a light source for emitting a light. An alignment mark is disposed on a substrate for receiving the light. The alignment mark includes a first pattern and a second pattern disposed on the substrate. The first pattern includes a first region and a second region. The second pattern includes a third region and a fourth region. The first region and the third region are symmetrical with respective to a symmetrical axis. The second region and the fourth region are symmetrical with respective to the symmetrical axis. The first region includes first mark lines parallel to each other. The second region includes second mark lines parallel to each other. A first pitch is disposed between the first mark lines adjacent to each other. A second pitch is disposed between the second mark lines adjacent to each other. The first pitch is different from the second pitch.

A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; a via disposed through the second level, where each of the second transistors includes a metal gate, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

The present disclosure provides a mask pattern for a semiconductor photolithography process and a semiconductor photolithography process. The mask pattern comprises: a pattern, the pattern comprising a light-transmitting area and a light-shielding area which are alternately arranged, the pattern having a boundary formed by an end portion of the light-transmitting area and an end portion of the light-shielding area, and an edge light-transmitting area being formed at the boundary. By the mask pattern of the present disclosure, a pattern with smooth edges can be formed on a wafer, and the edge roughness of the pattern is low, which meets the design requirements, thereby improving product quality and yield.

Disclosed is a method for determining a focus parameter value used to expose at least one structure on a substrate. The method comprises obtaining measurement data relating to a measurement of said at least one structure, wherein the at least one structure comprises a single periodic structure per measurement location and decomposing said measurement data into component data comprising one or more components of said measurement data. At least one of said components is processed to extract processed component data having a reduced dependence on non-focus related effects and a value for the focus parameter is determined from said processed component data. Associated apparatuses and patterning devices are also disclosed.