A sensor device provided in the disclosure includes a sensor substrate, a first transparent layer, a collimator layer, and a lens. The first transparent layer is disposed on the sensor substrate, wherein the first transparent layer defines an alignment structure. The collimator layer is disposed on the first transparent layer. The lens is disposed on the collimator layer.

One or more embodiments of the present disclosure are directed toward improved methods of fabricating a semiconductor device utilizing multi-level electron beam lithography (e-beam lithography), an alignment marker for multi-level e-beam lithography, and a semiconductor device including the alignment marker. A method of fabricating a semiconductor device may include: forming an alignment marker in a substrate, the alignment marker including tantalum; determining, utilizing a backscatter electron detector of an electron beam lithography tool, a location of an edge of the alignment marker based on an atomic number contrast between the alignment marker and the substrate; and forming, utilizing the electron beam lithography tool, at least one transistor in the substrate based on the location of the edge of the alignment marker.

A sensor device provided in the disclosure includes a sensor substrate, a first transparent layer, a collimator layer, and a lens. The first transparent layer is disposed on the sensor substrate, wherein the first transparent layer defines an alignment structure. The collimator layer is disposed on the first transparent layer. The lens is disposed on the collimator layer.

An overlay metrology target (T) is formed by a lithographic process. A first image (740(0)) of the target structure is obtained using with illuminating radiation having a first angular distribution, the first image being formed using radiation diffracted in a first direction (X) and radiation diffracted in a second direction (Y). A second image (740(R)) of the target structure using illuminating radiation having a second angular illumination distribution which the same as the first angular distribution, but rotated 90 degrees. The first image and the second image can be used together so as to discriminate between radiation diffracted in the first direction and radiation diffracted in the second direction by the same part of the target structure. This discrimination allows overlay and other asymmetry-related properties to be measured independently in X and Y, even in the presence of two-dimensional structures within the same part of the target structure.

A method for manufacturing semiconductor mark includes: providing a pattern having a peripheral edge corrected by Optical Proximity Correction (OPC); cutting multiple independent alignment sections from the pattern; and splicing the multiple alignment sections to form a semiconductor mark having a peripheral edge corrected by OPC.

A method includes forming a first photomask including N mask chip regions and a first mask scribe lane region surrounding each of the N mask chip regions, forming a second photomask including M mask chip regions and a second mask scribe lane region surrounding each of the M mask chip regions, performing a first semiconductor process including a first photolithography process using the first photomask on a semiconductor wafer; and performing a second semiconductor process including a second photolithography process using the second photomask on the semiconductor wafer. The first photolithography process is an extreme ultraviolet (EUV) photolithography process, the first photomask is an EUV photomask, N is a natural number of 2 or more, and M is two times N.

An apparatus and a method for forming alignment marks are disclosed. The method for forming alignment marks is a photolithography-free process and includes the following operations. A laser beam is provided. The laser beam is divided into a plurality of laser beams separated from each other. The plurality of laser beams is shaped into a plurality of patterned beams, so that the plurality of patterned beams is shaped with patterns corresponding to alignment marks. The plurality of patterned beams is projected onto a semiconductor wafer.

Embodiments described herein relate to substrate processing methods. More specifically, embodiments of the disclosure provide for an MRAM back end of the line integration process which utilizes a zero mark for improved patterning alignment. In one embodiment, the method includes fabricating a substrate having at least a bottom contact and a via extending from the bottom contact in a first region and etching a zero mark in the substrate in a second region apart from the first region. The method also includes depositing a touch layer over the substrate in the first region and the second region, depositing a memory stack over the touch layer in the first region and the second region, and depositing a hardmask over the memory stack layer in the first region and the second region.

The present disclosure is related to a method of forming a pattern, including the steps of: providing a structure including a substrate and a target layer, in which the target layer is disposed on the substrate, and the target layer includes a central area and a periphery area; forming a plurality of core patterns and a linear spacer pattern on the central area, in which a width of the linear spacer pattern is wider than 50 nm; covering a photoresist on the periphery area; removing a portion of the central area not covered by the plurality of core patterns and not covered by the linear spacer pattern to form a pattern in the central area, and removing the photoresist, the linear spacer pattern and the plurality of core patterns to expose the pattern.

Disclosed is a lithography process on a sample including at least one structure and covered by at least a lower layer of resist and a upper layer of resist the process including: using an optical device to image or determine, in reference to the optical device, a position of the selected structure and positions of markers integral with the sample; using an electron-beam device, imaging or determining the position of each marker in reference to the electron-beam device; deducing the position of the selected structure in reference to the electron-beam device; exposing to an electron beam the upper layer of resist above the position of the selected structure to remove all the thickness of the upper layer of resist above the position of the selected structure but none or only part of the thickness of the lower layer of resist above the position of the selected structure.