An overlay metrology target (T) is formed by a lithographic process. A first image (740(0)) of the target structure is obtained using with illuminating radiation having a first angular distribution, the first image being formed using radiation diffracted in a first direction (X) and radiation diffracted in a second direction (Y). A second image (740(R)) of the target structure using illuminating radiation having a second angular illumination distribution which the same as the first angular distribution, but rotated 90 degrees. The first image and the second image can be used together so as to discriminate between radiation diffracted in the first direction and radiation diffracted in the second direction by the same part of the target structure. This discrimination allows overlay and other asymmetry-related properties to be measured independently in X and Y, even in the presence of two-dimensional structures within the same part of the target structure.

In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

Metrology targets are formed by a lithographic process, each target comprising a bottom grating and a top grating. Overlay performance of the lithographic process can be measured by illuminating each target with radiation and observing asymmetry in diffracted radiation. Parameters of metrology recipe and target design are selected so as to maximize accuracy of measurement of overlay, rather than reproducibility. The method includes calculating at least one of a relative amplitude and a relative phase between (i) a first radiation component representing radiation diffracted by the top grating and (ii) a second radiation component representing radiation diffracted by the bottom grating after traveling through the top grating and intervening layers. The top grating design may be modified to bring the relative amplitude close to unity. The wavelength of illuminating radiation in the metrology recipe can be adjusted to bring the relative phase close to /2 or 3/2.

A microelectronic device is formed by loading a wafer, in which the microelectronic device is being formed, onto a pre-alignment stage for a wafer stepper. If the pre-alignment stage does not align the wafer properly using a notch pin, the wafer is loaded onto a wafer stepper stage of the wafer stepper. The wafer is positioned under a Field Image Alignment (FIA) camera of the wafer stepper, so that the FIA camera provides an image of the wafer notch. The wafer is rotated into a proper position. The wafer is transferred back to the pre-alignment stage. The wafer is aligned using the notch pin. The wafer is transferred to the wafer stepper stage. Fabrication is continued to form the microelectronic device.

A method includes establishing a simulation process for simulating fabrication of a structure on a wafer. The simulation process includes multiple simulation steps for simulating multiple wafer fabrication steps respectively, and further includes a step of testing the structure that produces a result representing quality of the structure. Each of the simulation steps has a respective adjustable process parameter. The method further includes specifying a respective workable range for each process parameter and running the simulation process in iterations using a wafer process simulator until the result becomes optimal. During the running of the simulation process, every two consecutive iterations either adjust two different process parameters within their workable ranges or adjust a same process parameter at opposite directions within its workable range.

On a substrate conforming to a layout method for a plurality of marks for detection using a plurality of mark detection systems of which the detection centers are arranged at a predetermined spacing along an X-axis direction, a plurality of shot areas are formed in both an X-axis direction and a Y-axis direction orthogonal thereto in an XY plane, and sets including at least two marks separated in the X-axis direction are repeatedly arranged along the X-axis direction at spacing of a length in the X-axis-direction of each shot area, and the marks belonging to each set are separated from each other in the X-axis direction by a spacing determined based arrangement in the X-axis direction of the plurality of mark detection systems and the length. It is thereby possible to reliably detect a plurality of marks on a substrate using a plurality of mark detection systems.

An apparatus for determining information relating to at least one target alignment mark in a semiconductor device substrate. The target alignment mark is initially at least partially obscured by an opaque carbon or metal layer on the substrate. The apparatus includes an energy delivery system configured to emit a laser beam for modifying at least one portion of the opaque layer to cause a phase change and/or chemical change in the at least one portion that increases the transparency of the portion. An optical signal can propagate through the modified portion to determine information relating to the target alignment mark.

Embodiments of the disclosure provides an apparatus for aligning layers of an integrated circuit (IC), the apparatus including: an insulator layer positioned above a semiconductor substrate; a first diffraction grating within a first region of the insulator layer, the first diffraction grating including a first grating material within the first region of the insulator layer; and a second diffraction grating within a second region of the insulator layer, the second grating including a second grating material within the second region of the insulator layer, wherein the second grating material is different from the first grating material, and wherein an optical contrast between the first and second grating materials is greater than an optical contrast between the second grating material and the insulator layer.

Some embodiments include provision of a mass of semiconductor material having a first region and a second region. A first pattern set is formed to extend across the first region, and a third pattern set is formed to extend across the second region. The first pattern set includes first lines and first trenches between the first lines. The third pattern set includes alignment marks. The first trenches are utilized to form rails from the semiconductor material within the first region. The alignment marks are parallel to the rails. A second pattern set is formed to extend across the first region, and a fourth pattern set is formed to extend across the second region. The second pattern set includes first openings, and the fourth pattern set includes second openings. The first openings are utilized to subdivide the rails into pillars. The second openings transform the alignment marks into an overlay pattern.

Embodiments of the disclosure provides an apparatus for aligning layers of an integrated circuit (IC), the apparatus including: an insulator layer positioned above a semiconductor substrate; a first diffraction grating within a first region of the insulator layer, the first diffraction grating including a first grating material within the first region of the insulator layer; and a second diffraction grating within a second region of the insulator layer, the second grating including a second grating material within the second region of the insulator layer, wherein the second grating material is different from the first grating material, and wherein an optical contrast between the first and second grating materials is greater than an optical contrast between the second grating material and the insulator layer.