A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.

According to one embodiment, in a position measuring method, alignment measurement in a light exposure process is executed by irradiating a first mark with light having a wavelength of 1, with respect to a processing object that includes a first layer and a second layer stacked above a substrate and a resist applied on the second layer. The first mark is provided in the first layer and includes a plurality of segments arranged at a pitch smaller than a resolution limit given by light having the wavelength of 1. Then, overlay measurement is executed by irradiating the first mark and a second mark with light having a wavelength of 2 shorter than the wavelength of 1. The second mark has been formed by performing a light exposure and development process to the resist, and includes a plurality of segments arranged at the pitch.

According to one embodiment, in a position measuring method, alignment measurement in a light exposure process is executed by irradiating a first mark with light having a wavelength of 1, with respect to a processing object that includes a first layer and a second layer stacked above a substrate and a resist applied on the second layer. The first mark is provided in the first layer and includes a plurality of segments arranged at a pitch smaller than a resolution limit given by light having the wavelength of 1. Then, overlay measurement is executed by irradiating the first mark and a second mark with light having a wavelength of 2 shorter than the wavelength of 1. The second mark has been formed by performing a light exposure and development process to the resist, and includes a plurality of segments arranged at the pitch.

A method including: subsequent to a first device lithographic step of a device patterning process, measuring a degraded metrology mark on an object and/or a device pattern feature associated with the degraded metrology mark, the degraded metrology mark arising at least in part from the first device lithographic step on the object; and prior to a second device lithographic step of the device patterning process on the object, creating a replacement metrology mark, for use in the patterning process in place of the degraded metrology mark, on the object.

In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.

A detection apparatus that detects a mark formed on a substrate is provided. The detection apparatus includes a substrate holder configured to hold the substrate, an optical system accommodated in the substrate holder, an image sensor configured to capture an image of the mark from the reverse surface side of the substrate through the optical system, and a processor configured to perform detection processing for the mark based on the image of the mark captured by the image sensor. The processor corrects a detection value of the mark based on the position of the mark on the substrate in the height direction and information concerning the telecentricity of the optical system.

Techniques are provided for fabricating and utilizing optically opaque non-planar alignment structures in non-die areas (e.g., kerf areas) of a wafer to align photomasks to die areas on the wafer. For example, an insulating layer is formed over non-die and die areas of the wafer. A non-planar alignment feature is formed in the insulating layer in the non-die area. An optically opaque layer stack is formed in the die and non-die areas of the wafer, which conformally covers the non-planar alignment feature to form an optically opaque non-planar alignment structure in the non-die area. A lithographic patterning process is performed to pattern the optically opaque layer stack in the die area, wherein the optically opaque non-planar alignment structure in the non-die area is utilized to align a photomask to the die area. The optically opaque non-planar alignment structure can include any type of non-planar structure having a stepped sidewall surface.

Disclosed is a lithography process on a sample including at least one structure and covered by at least a lower layer of resist and a upper layer of resist the process including: using an optical device to image or determine, in reference to the optical device, a position of the selected structure and positions of markers integral with the sample; using an electron-beam device, imaging or determining the position of each marker in reference to the electron-beam device; deducing the position of the selected structure in reference to the electron-beam device; exposing to an electron beam the upper layer of resist above the position of the selected structure to remove all the thickness of the upper layer of resist above the position of the selected structure but none or only part of the thickness of the lower layer of resist above the position of the selected structure.

Provided is a manufacturing method of a semiconductor apparatus including: detecting a position by detecting positional deviation of the upper surface mark and the lower surface mark, by acquiring an upper surface image obtained by observing the upper surface mark from above the upper surface of the semiconductor substrate and a lower surface image obtained by observing the lower surface mark through the semiconductor substrate from above the upper surface of the semiconductor substrate; and forming an element by forming a semiconductor element in the semiconductor substrate, where in a top view in which the upper surface mark and the lower surface mark are projected onto a plane parallel to the upper surface, one of the upper surface mark and the lower surface mark is larger than an other, and the one entirely covers the other.