Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.

A method includes forming a first photomask including N mask chip regions and a first mask scribe lane region surrounding each of the N mask chip regions, forming a second photomask including M mask chip regions and a second mask scribe lane region surrounding each of the M mask chip regions, performing a first semiconductor process including a first photolithography process using the first photomask on a semiconductor wafer; and performing a second semiconductor process including a second photolithography process using the second photomask on the semiconductor wafer. The first photolithography process is an extreme ultraviolet (EUV) photolithography process, the first photomask is an EUV photomask, N is a natural number of 2 or more, and M is two times N.

A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.

In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

According to an embodiment, a reflective liquid crystal display element includes a first substrate, an electronic circuit and an insulating layer including the electronic circuit formed on a surface of the first substrate, a plurality of reflection metal electrodes formed on a surface of the insulating layer, a plurality of spacers, a second substrate opposed to the first substrate with the plurality of spacers interposed therebetween, a plurality of color filters formed on a surface of a second substrate, the plurality of color filters corresponding to the plurality of reflection metal electrodes, a coating layer formed so as to cover the plurality of color filters, a transparent electrode formed on a surface of the coating layer, and a liquid crystal formed in a spatial area between the first and second substrates.

A method, including printing an apparatus mark onto a structure while the structure is at least partly within a lithographic apparatus. The structure may be part of, or is located on, a substrate table, but is separate from a substrate to be held by the apparatus. The method further includes measuring the apparatus mark using a sensor system within the apparatus.

Embodiments described herein relate to substrate processing methods. More specifically, embodiments of the disclosure provide for an MRAM back end of the line integration process which utilizes a zero mark for improved patterning alignment. In one embodiment, the method includes fabricating a substrate having at least a bottom contact and a via extending from the bottom contact in a first region and etching a zero mark in the substrate in a second region apart from the first region. The method also includes depositing a touch layer over the substrate in the first region and the second region, depositing a memory stack over the touch layer in the first region and the second region, and depositing a hardmask over the memory stack layer in the first region and the second region.

A mark forming method includes: forming recessed portion on a mark formation area of a substrate; coating the recessed portion with a polymer layer containing a block copolymer, allowing the polymer layer in the recessed portion to form a self-assembled area; selectively removing a portion of the self-assembled area; and forming a positioning mark by using the self-assembled area from which the portion thereof has been removed.

A lithography apparatus includes a formation unit that forms an alignment mark on a substrate by irradiating the substrate that includes a photosensitizer with light, and a transfer unit that aligns the substrate on the basis of the position of the alignment mark and that transfers a pattern to the substrate by illuminating the photosensitizer with exposure light. The formation unit irradiates a material of a grounding of the photosensitizer with irradiation light at a wavelength that differs from that of the exposure light and forms the alignment mark on the material by processing the material with energy of the irradiation light.

A method for recovering alignment marks in a mark layer of a substrate, the method including providing a substrate with a mark layer covered by a resist layer; forming alignment marks in the mark layer, wherein an alignment mark is formed by: exposing the resist layer to a patterned radiation beam thereby forming an alignment pattern in the resist; forming one or more recovery marks in the mark layer, wherein a recovery mark is formed by exposing the resist layer to at least a portion of the patterned radiation beam thereby forming an alignment pattern in a mark area of the resist and subsequently exposing the mark area of the resist, each time with a shifted patterned radiation beam until a substantial part of the mark area has been exposed.