A method of processing a wafer is provided. The method includes providing a reference plate below the wafer. The reference plate includes a reference pattern. The reference plate is imaged to capture an image of the reference pattern by directing light through the wafer. A first pattern is aligned using the image of the reference pattern. The first pattern is applied to a working surface of the wafer based on the aligning.

The present application provides a method for avoiding a damage to an overlay metrology mark, forming a plurality of raised silicon structures on an active area of a scribe line area on a silicon substrate, forming first to third dielectric layers on the silicon structure, and forming an axial structure of a fin and a spacer on the first to third dielectric layers; forming a shallow trench isolation (STI) area on the silicon substrate between the axial structures; removing a portion of the silicon structure along the height thereof on the scribe line area, the height of the residual silicon structure is 150-300 angstroms higher than that of the STI area; forming a plurality of dummy gates on the residual silicon structure on the scribe line, then applying a dielectric layer to fill a gap between the dummy gates, polishing the dielectric layer to expose the top of the dummy gate.

A 3D integrated circuit, the circuit including: a first level including a first wafer, the first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second level including a second wafer, the second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors, where the second level is bonded to the first level, where the bonded includes metal to metal bonding, where the bonded includes oxide to oxide bonding, and where at least one of the second transistors include a replacement gate.

The present application provides an alignment method for backside photolithography process of the wafer, the alignment method includes: cutting the wafer, and using at least two edges formed by cutting as the first alignment mark; bonding the front side of the wafer to the wafer pad to form a composite wafer; aligning the first alignment mark with the corresponding second alignment mark on the photomask for backside photolithography. This method is not limited by wafer thickness and material, and reduces the secondary input of the photolithography equipment; meanwhile, the probability of fragments of thin wafers in the photolithography process can be reduced, and the yield of the product is effectively improved.

A method of pattern alignment is provided. The method includes identifying a reference pattern positioned below a working surface of a wafer. The wafer is exposed to a first pattern of actinic radiation. The first pattern is a first component of a composite pattern. The first pattern of actinic radiation is aligned using the reference pattern. The wafer is exposed to a second pattern of actinic radiation. The second pattern is a second component of the composite pattern and exposed adjacent to the first pattern. The second pattern of actinic radiation is aligned with the first pattern of actinic radiation using the reference pattern.

A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; a via disposed through the second level, where each of the second transistors includes a metal gate, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

A semiconductor structure includes a device area that includes a first structure in a first layer having a top surface above a top surface of the first layer, and a second structure in a second layer on top of the first layer, where the first structure is pinned in the second structure; an overlay metrology area for optically evaluating an overlay error between the second and first structure, including: a third structure in the first layer, having a top surface above the top surface of the first layer, a fourth structure in the second layer, where the combination of the third and fourth structures mimics the combination of the first structure and the second structures, and a fifth structure in the first layer, for use as a reference structure.

A semiconductor device, including: a first memory cell including a first transistor; a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor self-aligned to the first transistor; and a plurality of junctionless transistors, where at least one of the junctionless transistors controls access to at least one of the memory cells.

The present invention provides a detection apparatus for detecting a position of a detection target including a diffraction grating pattern, comprising: an illuminator configured to illuminate the detection target with illumination light including a plurality of wavelengths; a wavelength selector including an incident surface on which diffracted light from the detection target is incident, and configured to select light of a specific wavelength from the diffracted light; and a detector configured to receive the light of the specific wavelength selected by the wavelength selector and detect the position of the detection target, wherein positions on the incident surface where light components of the plurality of wavelengths included in the illumination light are incident are different from each other, and wherein the wavelength selector controls each of the plurality of elements in accordance with the position on the incident surface.

A method for selecting an optimal set of locations for a measurement or feature on a substrate, the method includes: defining a first candidate solution of locations, defining a second candidate solution with locations based on modification of a coordinate in a solution domain of the first candidate solution, and selecting the first and/or second candidate solution as the optimal solution according to a constraint associated with the substrate.